ICS83940DYI IDT, Integrated Device Technology Inc, ICS83940DYI Datasheet - Page 2

ICS83940DYI

Manufacturer Part Number
ICS83940DYI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS83940DYI

Number Of Clock Inputs
2
Output Frequency
250MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
LQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS83940DYI-01LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS83940DYI-01LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
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Manufacturer:
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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Part Number:
ICS83940DYILFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
ICS83940DYILFT
Quantity:
1 734
ICS83940DI Data Sheet
ICS83940DYI REVISION C SEPTEMBER 7, 2010
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
R
R
C
R
1, 2, 12, 17, 25
IN
PULLUP
PULLDOWN
PD
OUT
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
9, 10, 11,
8, 16, 29
Number
7, 21
3
4
5
6
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Q17, Q16, Q15,
Q14, Q13, Q12,
LVCMOS_CLK
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
CLK_SEL
nPCLK
Name
PCLK
V
GND
V
DDO
DD
Output
Power
Power
Power
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Test Conditions
Description
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects PCLK, nPCLK inputs.
LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
Power supply pin.
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
2
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Minimum
18
©2010 Integrated Device Technology, Inc.
Typical
DD
51
51
4
6
/2 default when left floating.
Maximum
28
Units
k
k
pF
pF

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