P89C54X2BA NXP Semiconductors, P89C54X2BA Datasheet - Page 36

• Manufacturer Part Number: P89C54X2BA
• Manufacturer: NXP Semiconductors

Specifications of P89C54X2BA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
DC ELECTRICAL CHARACTERISTICS
T
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Capacitive loading on ports 0 and 2 may cause the V
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
5. See Figures 35 through 38 for I
6. This value applies to T
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
9. ALE is tested to V
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
2002 Jun 06
amb
SYMBOL PARAMETER
V
V
V
V
V
V
V
I
I
I
I
R
C
IL
TL
LI
CC
IL
IH
IH1
OL
OL1
OH
OH1
80C51 8-bit Flash microcontroller family
4K/8K/16K/32K Flash
RST
IO
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
maximum value when V
12-clock mode characteristics:
If I
test conditions.
(except EA is 25 pF).
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
= 0 C to +70 C or –40 C to +85 C; V
OL
Active mode:
Idle mode:
Maximum I
Maximum I
Maximum total I
exceeds the test condition, V
Input low voltage
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3
Output low voltage, port 0, ALE, PSEN
Output high voltage, ports 1, 2, 3
Output high voltage (port 0 in external bus
mode), ALE
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
Power supply current (see Figure 34):
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped
(see Figure 38 for conditions)
Internal reset pull-down resistor
Pin capacitance
OL
OL
per port pin:
per 8-bit port:
OH1
OL
9
, except when ALE is off then V
amb
for all outputs:
, PSEN
IN
10
is approximately 2 V.
11
= 0 C to +70 C. For T
(except EA)
3
I
I
CC
CC
CC
test conditions and Figure 34 for I
(MAX) = (8.5 + 0.62
(MAX) = (3.5 + 0.18
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
15 mA (*NOTE: This is 85 C specification.)
26 mA
71 mA
11
CC
8
3
= 5 V 10%; V
OL
amb
7, 8
must be externally limited as follows:
= –40 C to +85 C, I
OH
OH
6
on ALE and PSEN to momentarily fall below the V
is the voltage specification.
TEST
CONDITIONS
4.5 V < V
–
–
V
V
V
V
V
V
0.45 < V
T
T
–
–
FREQ. [MHz])mA
FREQ. [MHz])mA
amb
amb
CC
CC
CC
CC
IN
IN
SS
= 0.4 V
= 2.0 V; See note 4
= 4.5 V; I
= 4.5 V; I
= 4.5 V; I
= 4.5 V; I
= 0 C to 70 C
= –40 C to +85 C
= 0 V (20/33 MHz max. CPU clock)
IN
CC
36
< V
CC
< 5.5 V
OL
OL
OH
OH
vs. Frequency.
CC
TL
= 1.6 mA
= 3.2 mA
= –30 A
= –3.2 mA
– 0.3
= –750
2
2
.
LIMITS
MIN
–0.5
0.2 V
0.7 V
–
–
V
V
–1
–
–
40
–
CC
CC
P89C51X2/52X2/54X2/58X2
OL
OL
– 0.7
– 0.7
CC
CC
s of ALE and ports 1 and 3. The noise is due
can exceed these conditions provided that no
+0.9
TYP
15
CC
1
–0.7 specification when the
MAX
0.2 V
V
V
0.4
0.4
–
–
–50
–650
100
125
225
15
10
CC
CC
+0.5
+0.5
CC
–0.1
Preliminary data
UNIT
V
V
V
V
V
V
V
k
pF
A
A
A
A
A