71V30L55TF IDT, Integrated Device Technology Inc, 71V30L55TF Datasheet
71V30L55TF
Specifications of 71V30L55TF
Related parts for 71V30L55TF
71V30L55TF Summary of contents
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Features ◆ High-speed access – Commercial: 25/35/55ns (max.) ◆ Low-power operation – IDT71V30S — Active: 375mW (typ.) — Standby: 5mW (typ.) – IDT71V30L — Active: 375mW (typ.) — Standby: 1mW (typ.) Functional Block Diagram ...
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... Description The IDT71V30 is a high-speed Dual-Port Static RAM. The IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port SRAM. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND Temperature T BIAS Under Bias T Storage STG Temperature (3) T Junction Temperature JN DC Output ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter I Dynamic Operating Current (Both Ports Active) Outputs Disabled Standby ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT BUSY 435Ω INT Figure 1. AC Output Test Load AC ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Timing Waveform of Read Cycle No. 1, Either Side ADDRESS t OH DATA OUT PREVIOUS DATA VALID BUSY OUT NOTES and ...
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... Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for t must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH temperature, the actual t ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Timing Waveform of Write Cycle No. 1,(R/W Controlled Timing) ADDRESS R/W DATA (4) OUT DATA IN Timing Waveform of Write Cycle No Controlled ...
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... BUSY Disable to Valid Data (3) t BDD NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY" ensure that the earlier of the two ports wins calculated parameter and is the greater BDD 4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”. ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Timing Waveform of Write with BUSY R/W BUSY R/W NOTES: must be met for BUSY BUSY is asserted on port 'B' blocking R/W , until BUSY ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Truth Tables Table I — Non-Contention Read/Write Control (1) Left or Right Port DATA ...
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... SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed write ...
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IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Ordering Information XXXX A 999 A Device Type Power Speed Package NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green ...