IDT70V9279S15PRF IDT, Integrated Device Technology Inc, IDT70V9279S15PRF Datasheet - Page 12

• Manufacturer Part Number: IDT70V9279S15PRF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70V9279S15PRF

• Density: 512Kb
• Access Time (max): 15ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 28.5MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 220mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Word Size: 16b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Timing Waveform with Port-to-Port Flow-Through Read
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE
3. OE = V
4. If t
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform of Left Port Write to Pipelined Right Port Read
NOTES:
1. CE
2. OE = V
3. If t
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
If t
t
will be t
CO
ADDRESS
ADDRESS
CCS
CCS
0
DATA
CO
0
, UB, LB, and ADS = V
, BE
+ 2 t
DATA
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
< maximum specified, then data from right port READ is not valid until the maximum specified for t
> maximum specified, then data from right port READ is not valid until t
IL
IL
CO
CLK
CLK
R/W
R/W
n
OUT"B"
CYC2
for the Right Port, which is being read from. OE = V
, and ADS = V
ADDRESS
ADDRESS
for Port "B", which is being read from. OE = V
IN"A"
+ t
DATA
"A"
"A"
"B"
"B"
"B"
DATA
"A
CYC2
"
+ t
CLK
R/W
CLK
R/W
CD2
OUT "B"
+ t
IN "A"
). If t
"A"
"A"
"A"
"B"
"B"
"B"
CD2
IL
CO
).
; CE
IL
t
t
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
; CE
t
MATCH
VALID
SW
SD
SA
1
, CNTEN, and REPEAT = V
t
t
MATCH
SW
1
SA
, CNTEN, and CNTRST = V
t
t
t
HW
HA
HD
t
t
HW
HA
MATCH
t
t
VALID
t
SA
SD
SW
t
CO
MATCH
t
t
SA
SW
t
t
t
(3)
HA
HD
HW
t
DC
t
t
HW
HA
t
CCS
IH
IH
for Port "A", which is being written to.
(4)
t
.
CWDD
IH
IH
.
for the Left Port, which is being written to.
t
CD1
(4)
MATCH
NO
6.42
12
CCS
+ t
CD1
t
CD2
. t
CWDD
VALID
does not apply in this case.
Industrial and Commercial Temperature Ranges
MATCH
NO
MATCH
CWDD
NO
VALID
.
MATCH
NO
t
DC
(1,2,3,5)
t
CD1
t
DC
3743 drw 10
(1,2,4)
VALID
3743 drw 09
,