K4D263238I-UC50 Samsung Semiconductor, K4D263238I-UC50 Datasheet
K4D263238I-UC50
Specifications of K4D263238I-UC50
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K4D263238I-UC50 Summary of contents
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... K4D263238I-UC 128Mbit GDDR SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4D263238I-UC Revision History Revision Month Year 0.0 September 2005 0.1 October 2005 1.0 October 2005 1.1 January 2006 1.2 November 2006 - Target Spec - Defined target specification - Added current spec - Finalized SPEC - Modified ICC6 value from 7mA to 10mA - Corrected typo - 2 - 128M GDDR SDRAM History Rev ...
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... Differential clock input • Write Interrupted by Read function ORDERING INFORMATION Part NO. K4D263238I-UC40 K4D263238I-UC50 K4D263238I-QC is the Leaded package part number. GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238I is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 1,048,576 words by 32 bits, fabricated with SAMSUNG extremely high performance ...
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... K4D263238I-UC PIN CONFIGURATION 81 DQ29 VSSQ 82 83 DQ30 DQ31 84 85 VSS VDDQ 86 87 N.C N N.C N VSSQ RFU 93 94 DQS VDDQ 95 96 VDD DQ0 97 DQ1 98 99 VSSQ DQ2 100 PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS ...
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... K4D263238I-UC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF MCL Must Connect Low *1 : The timing reference point for the differential clocking is the cross point of CK and CK. ...
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... K4D263238I-UC BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS ...
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... K4D263238I-UC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D263238I-UC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D263238I-UC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... K4D263238I-UC ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... K4D263238I-UC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current in I CC3 in Non Power-down mode ...
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... K4D263238I-UC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter Input capacitance( CK ...
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... K4D263238I-UC AC CHARACTERISTICS Parameter CK cycle time CL=3 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble ...
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... K4D263238I-UC Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
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... Note :1 For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K4D263238I-UC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 K4D263238I-UC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3 * 183/166MHz were supported in K4D263238I-UC50 -40 Symbol Min Max tRC 15 - tRFC 17 - tRAS 10 100K tRCDRD 5 - tRCDWR ...
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... K4D263238I-UC Simplified Timing(2) @ BL=4, CL CK, CK BA[1:0] BAa BAa Ra Ra A8/AP ADDR Ra Ca (A0~A7, A9~,A11) WE DQS Da0 Da1 Da2 Da3 DQ DM ACTIVEA WRITEA COMMAND tRCD tRAS Normal Write Burst (@ BL= BAa BAa Ra Ra PRECH ACTIVEA tRP tRC Multi Bank Interleaving Write Burst - 16 - 128M GDDR SDRAM ...
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... K4D263238I-UC PACKAGE DIMENSIONS (TQFP) #100 #1 0.825 17.20 ± 0.20 14.00 ± 0.10 23.20 ± 0.20 20.00 ± 0.10 0.30 ± 0.65 0.08 0.13 MAX 1.00 ± 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 ± 0. 128M GDDR SDRAM Dimensions in Millimeters ° ...