LP3952RLX National Semiconductor, LP3952RLX Datasheet - Page 25

• Manufacturer Part Number: LP3952RLX
• Manufacturer: National Semiconductor

Specifications of LP3952RLX

• Operating Supply Voltage (typ): 3.3/5V
• Number Of Segments: 6
• Operating Temperature (min): -30C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Pin Count: 36
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Not Compliant

LOGIC INPUTS ADDR_SEL, NRST, SCL, PWM, SDA
V
V
I
f
LOGIC OUTPUT SDA
V
I
L
SCL
L
IL
IH
OL
Symbol
Logic Interface Electrical Characteristics
(1.65V
Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption.
I
INTERFACE BUS OVERVIEW
The I
cess to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bi-direc-
tional communications between the devices connected to the
bus. The two interface lines are the Serial Data Line (SDA),
and the Serial Clock Line (SCL). These lines should be con-
nected to a positive supply, via a pull-up resistor and remain
HIGH even when the bus is idle. Every device on the bus is
assigned a unique address and acts as either a Master or a
Slave depending on whether it generates or receives the se-
rial clock (SCL).
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL). Con-
sequently, throughout the clock’s high period, the data should
remain stable. Any changes on the SDA line during the high
state of the SCL and in the middle of a transaction, aborts the
current transaction. New data should be sent during the low
SCL state. This protocol permits a single data line to transfer
both command/control information and data using the syn-
chronous serial clock.
I
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while SCL line is HIGH.
2
2
2
C DATA VALIDITY
C START AND STOP CONDITIONS
C Compatible Interface
2
2
C session. START condition is defined as SDA signal
C compatible synchronous serial interface provides ac-
≤
V
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
Output Low Level
Output Leakage Current V
DDIO
≤
I
2
Parameter
V
C Signals: Data Validity
DD1,2
V) (Unless otherwise noted).
I
SDA
SDA
= 3 mA
= 2.8V
Conditions
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25
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
START and STOP bits. The I
after START condition and free after STOP condition. During
data transmission, I
conditions. First START and repeated START conditions are
equivalent, function-wise.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP3952 address is
54h or 55H as selected with ADDR_SEL pin. I
LP3952 is 54H when ADDR_SEL=0 and 55H when
ADDR_SEL=1. For the eighth bit, a “0” indicates a WRITE
and a “1” indicates a READ. The second byte selects the reg-
ister to which the data will be written. The third byte contains
data to write to the selected register.
0.8×V
−1.0
Min
DDIO
th
clock pulse, signifying an acknowledge. A
2
C master can generate repeated START
I
2
C Chip Address
Typ
0.3
2
C bus is considered to be busy
2
2
C master sends a chip ad-
C master always generates
0.2×V
Max
400
1.0
0.5
1.0
DDIO
2
C address for
www.national.com
30023850
30023851
Units
kHz
μA
μA
V
V
V