AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 34

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

34
CACHE is a cycle definition pin used when in Write-back
mode (CACHE floats in Write-through mode). For pro-
cessor-initiated cycles, the signal indicates:
CACHE is asserted for cacheable reads, cacheable
code fetches, and write-backs/copy-backs. CACHE is
deasserted for non-cacheable reads, translation looka-
side buffer (TLB) replacements, locked cycles (except
for write-back cycles generated by an external snoop
operation that interrupts a locked read/modify/write se-
quence), I/O cycles, special cycles, and write-throughs.
CACHE is driven to its valid level in the same clock as
the assertion of ADS and remains valid until the next
RDY or BRDY assertion. The CACHE output pin floats
one clock after BOFF is asserted. Additionally, the signal
floats when HLDA is asserted.
The following steps describe the burst write sequence:
1. The access is started by asserting: ADS = 0, M/IO
2. In the second clock cycle, BLAST is 1 to indicate
3. The burst write access is finished when BLAST is
When the RDY signal is returned instead of the BRDY
signal, the Enhanced Am486DX microprocessors halt
the burst cycle and proceeds with the standard non-
burst cycle.
3.10.1 Locked Accesses
Locked accesses of Enhanced Am486DX microproces-
sors occur for read-modify-write operations and inter-
rupt acknowledge cycles. The timing is identical to the
standard 486DX microprocessor, although the state
transitions differ. Unlike processor-initiated accesses,
state transitions for locked accesses are seen by all
processors in the system. Any locked read or write gen-
erates an external bus cycle, regardless of cache hit or
miss. During locked cycles, the processor does not rec-
ognize a HOLD request, but it does recognize BOFF
and AHOLD requests.
Locked read operations always read data from the ex-
ternal memory, regardless of whether the data is in the
cache. In the event that the data is in the cache and
unmodified, the cache line is invalidated and an external
read operation is performed. The data from the external
memory is used instead of the data in the cache, thus
ensuring that the locked read is seen by all other bus
masters. If a locked read occurs, the data is in the cache,
and it is modified. The microprocessor first copies back
For a read cycle, the internal cacheability of the cycle
For a write cycle, a burst write-back or copy-back, if
KEN is asserted (for linefills).
= 1, W/R = 1, CACHE = 0. The address offset always
is 0, so the burst write always starts on a cache line
boundary. CACHE transitions High (inactive) after
the first BRDY.
that the burst is not finished.
0 and BRDY is 0.
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
the data to external memory, invalidates the cache line,
and then performs a read operation to the same location,
thus ensuring that the locked read is seen by all other
bus masters. At no time is the data in the cache used
directly by the microprocessor or a locked read opera-
tion before reading the data from external memory.
Since locked cycles always begin with a locked read
access, and locked read cycles always invalidate a
cache line, a locked write cycle to a valid cache line,
either modified or unmodified, does not occur.
3.10.2 Serialization
Locked accesses are totally serialized:
3.10.3 PLOCK Operation in Write-Through Mode
As described on page 15, PLOCK is only used in Write-
through mode; the signal is driven inactive in Write-back
mode. In Write-through mode, the processor drives
PLOCK Low to indicate that the current bus transaction
requires more than one bus cycle. The CPU continues
to drive the signal Low until the transaction is completed,
whether or not RDY or BRDY is returned. Refer to the
pin description for additional information.
4
4.1
The Enhanced Am486DX microprocessors are driven
by a 1x clock that relies on phased-lock loop (PLL) to
generate the two internal clock phases: phase one and
phase two. The rising edge of CLK corresponds to the
start of phase one (ph1). All external timing parameters
are specified relative to the rising edge of CLK.
4.2
The Enhanced Am486DX microprocessors also provide
an interrupt mechanism, STPCLK, that allows system
hardware to control the power consumption of the CPU
by stopping the internal clock to the CPU core in a se-
quenced manner. The first low-power state is called the
Stop Grant state. If the CLK input is completely stopped,
the CPU enters into the Stop Clock state (the lowest
power state). When the CPU recognizes a STPCLK in-
terrupt, the processor:
All reads and writes in the write buffer that precede
the locked access are issued on the bus before the
first locked access is executed.
No read or write after the last locked access is issued
internally or on the bus until the final RDY or BRDY
for all locked accesses.
It is possible to get a locked read, write-back, locked
write cycle.
Stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt)
Waits for completion of cache flush
Stops the pre-fetch unit
CLOCK CONTROL
Clock Generation
Stop Clock