M68AW127BM70MC6T STMicroelectronics, M68AW127BM70MC6T Datasheet - Page 7

• Manufacturer Part Number: M68AW127BM70MC6T
• Manufacturer: STMicroelectronics

Specifications of M68AW127BM70MC6T

• Density: 1Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: SO
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 15mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

OPERATION
The M68AW127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
Read Mode
The M68AW127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
Write Mode
The M68AW127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
t
by the latter occurring edge.
Table 2. Operating Modes
X = V
AVWL
Read
Read
Write
Deselect
Deselect
IH
or V
and t
Operation
IL
.
AVEH
, respectively, and is determined
V
V
V
V
E1
X
IH
IL
IL
IL
V
V
V
V
E2
X
IH
IH
IH
IL
V
V
V
W
X
X
IH
IH
IL
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 2).
within t
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(t
may be indeterminate at t
lines will always be valid at t
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within t
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
the rising edge of Write Enable, or for t
the rising edge of E1, whichever occurs first, and
remain valid for t
ELQV
V
V
or t
AVQV
G
X
X
X
IH
IL
GLQV
after the last stable address, provid-
) rather than the address. Data out
WLQZ
Data Output
WHDX
Data Input
DQ0-DQ7
Hi-Z
Hi-Z
Hi-Z
of its falling edge. Care must
or t
ELQX
EHDX
AVQV
and t
.
.
Standby (I
Standby (I
M68AW127B
Active (I
Active (I
Active (I
GLQX
DVWH
Power
DVEH
, but data
CC
CC
CC
before
before
SB
SB
)
)
)
)
)
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