LH28F128BFHT-PTTL75A Sharp Electronics, LH28F128BFHT-PTTL75A Datasheet

LH28F128BFHT-PTTL75A

Manufacturer Part Number
LH28F128BFHT-PTTL75A
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F128BFHT-PTTL75A

Cell Type
NOR
Density
128Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Top
Address Bus
23b
Operating Supply Voltage (typ)
3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.3/9 to 10V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.3V
Word Size
16b
Number Of Words
8M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Compliant

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Part Number:
LH28F128BFHT-PTTL75A
Manufacturer:
LATTICE
Quantity:
1 001
P
S
RODUCT
PECIFICATION
Integrated Circuits Group
LH28F128BFHT-PTTL75A
Flash Memory
128M (8Mb x 16)
(Model Number: LHF12F16)
Spec. Issue Date: June 7, 2004
Spec No: FM046010

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LH28F128BFHT-PTTL75A Summary of contents

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... P S RODUCT PECIFICATION LH28F128BFHT-PTTL75A Flash Memory 128M (8Mb x 16) (Model Number: LHF12F16) Spec. Issue Date: June 7, 2004 Spec No: FM046010 Integrated Circuits Group ...

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...

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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered herein, ...

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TSOP (Normal Bend) Pinout ....................... 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with 6 Planes........................................ 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 9 OTP Block Address Map for OTP Program............. 10 ...

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... LH28F128BFHT-PTTL75A Page Mode Dual Work Flash MEMORY 128-M density with 16-bit I/O Interface High Performance Reads • 75/25ns 8-Word Page Mode 6-Plane Dual Work Operation • Read operations are available during Block Erase or (Page Buffer) Program between two different Planes • Plane Architecture: ...

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WE# 13 RST ...

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... DEVICE POWER SUPPLY (2.7V-3.3V): With V V SUPPLY flash memory are inhibited. Device operations at invalid V CC Characteristics) produce spurious results and should not be attempted. INPUT/OUTPUT POWER SUPPLY (2.7V-3.3V): Power supply for all input/output V ...

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Table 2. Simultaneous Operation Modes Allowed with 6 Planes IF ONE Read Read Read PLANE IS: Array ID/OTP Status Read Array X X Read ID/OTP X X Read Status X X Read Query X X Word Program X X Page ...

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LHF12F16 [ 278000H - 27FFFFH 32-Kword Block 79 270000H - 277FFFH 32-Kword Block 78 268000H - 26FFFFH 32-Kword Block 77 260000H - 267FFFH 32-Kword Block 76 258000H - 25FFFFH 32-Kword Block 75 250000H - 257FFFH 32-Kword ...

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LHF12F16 [ 578000H - 57FFFFH 32-Kword Block 175 570000H - 577FFFH 32-Kword Block 174 568000H - 56FFFFH 32-Kword Block 173 560000H - 567FFFH 32-Kword Block 172 558000H - 55FFFFH 32-Kword Block 171 550000H - 557FFFH 32-Kword ...

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LHF12F16 [ 7FF000H - 7FFFFFH 4-Kword Block 262 7FE000H - 7FEFFFH 4-Kword Block 261 7FD000H - 7FDFFFH 4-Kword Block 260 7FC000H - 7FCFFFH 4-Kword Block 259 4-Kword Block 258 7FB000H - 7FBFFFH 7FA000H - 7FAFFFH 4-Kword ...

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Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down OTP OTP Lock OTP NOTES: ...

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LHF12F16 [ 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ - Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP ...

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... Refer to Table 5 for valid D during a write operation Never hold OE# low and WE# low at the same timing. 7. Query code = Common Flash Interface (CFI) code. 8. RY/BY when the WSM (Write State Machine) is executing internal block erase, full chip erase, OL (page buffer) program or OTP program algorithms High Z during when the WSM is not busy, in block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend mode, or reset mode ...

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... Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code and the data within OTP block (See Table 3). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST ...

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Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H the program operation ...

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Table 6. Functions of Block Lock Current State (1) State WP#/ACC DQ 1 [000 ( [001] [011 [100 ( [101] ( [110] [111 NOTES ...

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Table 8. Block Locking State Transitions upon WP#/ACC Transition Current State Previous State State WP#/ACC - [000 [001] 0 (2) [110] [011] 0 Other than (2) [110] - [100 [101 [110 [111] ...

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GWSMS GBESS GBEFCES PWSMS GBESS GBEFCES 7 6 SR.7 = PLANE WRITE STATE MACHINE STATUS (PWSMS Ready 0 = Busy SR.6 = GLOBAL BLOCK ERASE SUSPEND STATUS (GBESS Block Erase Suspended 0 = ...

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Table 9.2. Status Register Definition (Continued) SR.15 = GLOBAL WRITE STATE MACHINE STATUS (GWSMS Ready 0 = Busy SR.14 = GLOBAL BLOCK ERASE SUSPEND STATUS (GBESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.13 ...

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SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ...

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Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...-40°C to +85°C Storage Temperature During under Bias............................... -40°C to +85°C During non Bias................................ -65°C to +125°C Voltage On Any Pin (except ...

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Capacitance (T =+25°C, f=1MHz) A Parameter Symbol Input Capacitance C WP#/ACC Input Capacitance C Output Capacitance C NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CCQ INPUT 0.0 AC test inputs are driven at ...

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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Automatic Power CC I CCAS Current I V Reset Current CCD CC Average V Read CC Current Normal ...

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Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH WP#/ACC during Block Erase, Full V Chip Erase, (Page Buffer) Program or ACCH OTP Program Operations V V ...

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AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to ...

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(A) 22 EHEL V IH (E) CE AVEL t t GHGL V IH OE# ( (W) WE High (D/Q) 15-0 V ...

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(A) 22 (A) 2 CE# ( OE# ( WE# ( High (D/Q) 15-0 V ...

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(A) 22 AVQV V IH VALID A (A) 2-0 ADDRESS CE# ( ELQV V IH OE# ( WE# ( GLQX ...

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AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t (t ...

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NOTE 1 NOTE VALID A (A) 22-0 ADDRESS (E) CE ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# (W) V ...

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Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V ...

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Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4-Kword Parameter Block t WPB Program Time 32-Kword Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...

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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...

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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...

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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...

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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...

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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...

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