ICS8725AM-21 IDT, Integrated Device Technology Inc, ICS8725AM-21 Datasheet - Page 12

• Manufacturer Part Number: ICS8725AM-21
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay PLL Clock Generatorr

Specifications of ICS8725AM-21

• Number Of Elements: 1
• Supply Current: 137mA
• Pll Input Freq (min): 31.25MHz
• Pll Input Freq (max): 630MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SOIC
• Output Frequency Range: Up to 630MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

Schematic Example
Figure 4 shows a schematic example of the ICS8725-21. In this
example, the input is driven by an HCSL driver. The zero delay
buffer is configured to operate at 155.52MHz input and 77.75MHz
output. The logic control pins are configured as follows:
SEL[3:0] = 0101
PLL_SEL = 1
Figure 4. ICS8725-21 HSTL Buffer Schematic Example
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
ICS8725-21
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
3.3V
RU3
1K
RD3
SP
HCSL
VDD
RU4
1K
RD4
SP
SP = Space (i.e. not intstalled)
Zo = 50 Ohm
Zo = 50 Ohm
RU5
SP
RD5
1K
(155.5 MHz)
RU6
1K
RD6
SP
RU7
SP
RD7
1K
R8
50
SEL0
SEL1
SEL2
SEL3
PLL_SEL
R9
50
SEL2
R1
50
VDD
VDD=3.3V
VDDO=1.8V
SEL[3:0] = 0101,
Divide by 2
R2
50
ICS8725-21
10
1
2
3
4
5
6
7
8
9
U1
CLK
nCLK
MR
VDD
nFB_IN
FB_IN
SEL2
GND
nQFB
QFB
12
For ICS8725-21, the decoupling capacitors should be physically
located near the power pin.
PLL_SEL
VDDO
VDDA
SEL1
SEL0
SEL3
VDD
nQ
nc
Q
Bypass capacitors located
near the power pins
(U1-4)
20
19
18
17
16
15
14
13
12
11
0.1uF
C3
VDDO
0.1uF
C1
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDD
(U1-17)
(77.75 MHz)
ICS8725AM-21 REV. A FEBRUARY 27, 2008
0.1uF
C2
Zo = 50 Ohm
VDDA
0.01u
Zo = 50 Ohm
C11
R4
50
10u
C16
10
R7
VDD
LVHSTL_input
R5
50
+
-