CY7C187-25VC Cypress Semiconductor Corp, CY7C187-25VC Datasheet
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CY7C187-25VC
Specifications of CY7C187-25VC
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CY7C187-25VC Summary of contents
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... OUT The output pin stays in high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C187 utilizes a die coat to insure alpha immunity. SOJ DI Top View ...
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... V IN Test Conditions T = 25° MHz 5. 329 Ω 3.0V 5V GND R2 202 Ω INCLUDING JIG AND SCOPE C187–4 (b) Equivalent to: power-up, otherwise I CC CY7C187 .........................................–0.5V to +7.0V Ambient Temperature V CC ° ° 5V ± 10 +70 C -15 -25 and -35 Max. Min. Max. Unit 2.4 V 0.4 0 2.2 ...
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... HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write HIGH for read cycle. 10. Device is continuously selected Document #: 38-05044 Rev. *A [5] -15 Min. Max. Min OHA is less than t for any given device. HZCE LZCE CY7C187 -25 -35 Max. Min. Max. Unit DATA VALID C187–6 Page [+] Feedback ...
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... DATA IN DATA OUT DATA UNDEFINED Note: 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05044 Rev DATA VALID 50 SCE PWE t SD DATA VALID t HZWE CY7C187 t HZCE HIGH IMPEDANCE t PD ICC 50% ISB C187– LZWE HIGH IMPEDANCE C187–8 Page [+] Feedback ...
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... IN 0 0.0 –55 25 125 AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 V =5.0V CC 0.8 0.6 –55 25 125 AMBIENT TEMPERATURE (°C) CY7C187 C187–9 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. =25° 0.0 1.0 2.0 3.0 4 ...
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... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. =25°C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) Pin Number Deselect/Power-Down Read Write CY7C187 NORMALIZED I vs.CYCLE TIME CC 1.25 V =5. =25° =0.5V CC 1.00 0.75 0. CYCLE FREQUENCY (MHz) Mode Page [+] Feedback ...
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... Ordering Information Speed (ns) Ordering Code 15 CY7C187-15PXC 25 CY7C187-25PC CY7C187-25VC CY7C187-25VXC 35 CY7C187-35VXC Package Diagrams 11 12 1.070 1.120 0.140 0.190 0.115 0.160 0.090 0.110 Document #: 38-05044 Rev. *A Package Package Diagram 51-85012 22-pin (300-Mil) Molded DIP (Pb-free) 51-85012 22-pin (300-Mil) Molded DIP 51-85030 24-pin (300-Mil) Molded SOJ ...
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... SOJ (51-85030) PIN DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088 0.291[7.39] 0.330[8.38] PACKAGE WEIGHT 0.75gms 0.300[7.62] 0.350[8.89] V24.3 24 VZ24.3 SEATING PLANE 0.120[3.05] 0.140[3.55] 0.004[0.10] 0.025[0.63] MIN. CY7C187 MIN. MAX. PART # STANDARD PKG. LEAD FREE PKG. 0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91] 51-85030-*B Page [+] Feedback ...
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... Document History Page Document Title: CY7C187 64K x 1 Static RAM Document Number: 38-05044 Issue Orig. of REV. ECN NO. Date Change ** 107146 09/10/01 SZV *A 486744 See ECN NXR Document #: 38-05044 Rev. *A Description of Change Change from Spec number: 38-00038 to 38-05044 Removed 20 ns speed bin ...