CY7C1019CV33-15ZI Cypress Semiconductor Corp, CY7C1019CV33-15ZI Datasheet

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CY7C1019CV33-15ZI

Manufacturer Part Number
CY7C1019CV33-15ZI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1019CV33-15ZI

Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *D
Features
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
• Pin and function compatible with CY7C1019BV33
• High speed
• CMOS for optimum speed/power
• Data retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 32-pin TSOP II and 400-mil SOJ package
Logic Block Diagram
WE
CE
OE
— t
A
A
A
A
A
A
A
A
A
AA
0
1
2
3
4
5
6
7
8
= 8, 10, 12, 15 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
POWER
DOWN
7C1019CV33-8
3901 North First Street
85
8
5
7C1019CV33-10
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019CV33 is available in a standard 32-pin TSOP
II and 400-mil-wide SOJ.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
10
80
5
0
through I/O
San Jose
7C1019CV33-12
I/O
I/O
V
V
I/O
I/O
WE
128K x 8 Static RAM
CE
CC
A
A
A
A
A
A
A
A
SS
Pin Configuration
7
0
1
2
0
1
2
3
4
5
6
3
12
75
7
5
,
) is then written into the location
CA 95134
SOJ/TSOP II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Top View
0
0
Revised December 16, 2002
through I/O
through A
CY7C1019CV33
7C1019CV33-15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15
70
16
7
5
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
) are placed in a
).
408-943-2600
SS
CC
16
15
14
13
12
11
10
9
8
7
6
5
4
Unit
mA
mA
ns

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CY7C1019CV33-15ZI Summary of contents

Page 1

... I/O pins. The eight input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019CV33 is available in a standard 32-pin TSOP II and 400-mil-wide SOJ. I/O 0 I/O 1 ...

Page 2

... IN IL MAX Max > V – 0.3V > V – 0.3V < 0.3V Test Conditions T = 25° MHz 5.0V CC CY7C1019CV33 Ambient Temperature 0°C to +70°C – +85 C 7C1019CV33 7C1019CV33 7C1019CV33 -10 -12 -15 Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.0 V 2.0 V 2.0 ...

Page 3

... High-Z characteristics: 90% 10% (c) Fall Time: 1 V/ns Over the Operating Range 7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15 Min. Max. Min less than less than t HZCE LZCE HZOE CY7C1019CV33 R 317 3.3V OUTPUT 351 (b) R 317 3.3V OUTPUT 5 pF 351 R2 (d) Max. Min. Max. Min ...

Page 4

... Data I/O is high impedance 15 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05130 Rev OHA ACE t DOE t LZOE 50 SCE PWE DATA VALID . IL CY7C1019CV33 DATA VALID t HZOE t HZCE DATA VALID t PD 50% t SCE HIGH IMPEDANCE ICC ISB Page ...

Page 5

... During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05130 Rev. *D [14, 15 SCE PWE t SD DATA [15 SCE PWE t HZWE –I/O Mode 0 7 Power-Down Read Write Selected, Outputs Disabled CY7C1019CV33 VALID DATA VALID t LZWE Power Standby (I SB Active (I CC Active (I CC Active ( Page ...

Page 6

... CY7C1019CV33-8VI 10 CY7C1019CV33-10VC CY7C1019CV33-10ZC CY7C1019CV33-10VI CY7C1019CV33-10ZI 12 CY7C1019CV33-12VC CY7C1019CV33-12ZC CY7C1019CV33-12VI CY7C1019CV33-12ZI 15 CY7C1019CV33-15VC CY7C1019CV33-15ZC CY7C1019CV33-15VI CY7C1019CV33-15ZI Package Diagram Document #: 38-05130 Rev. *D Package Name Package Type V33 32-Lead 400-Mil Molded SOJ V33 32-Lead 400-Mil Molded SOJ V33 32-Lead 400-Mil Molded SOJ ZS32 32-Lead TSOP II V33 ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-lead TSOP II ZS32 CY7C1019CV33 51-85095-** Page ...

Page 8

... Document History Page Document Title: CY7C1019CV33 128K x 8 Static RAM Document Number: 38-05130 Issue REV. ECN NO. Date ** 109245 12/16/01 *A 113431 04/10/02 *B 115047 08/01/02 *C 119796 10/11/02 *D 123030 12/17/02 Document #: 38-05130 Rev. *D Orig. of Change HGK New Data Sheet NSL AC Test Loads split based on speed. ...

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