CY7C1018CV33-10VC Cypress Semiconductor Corp, CY7C1018CV33-10VC Datasheet

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CY7C1018CV33-10VC

Manufacturer Part Number
CY7C1018CV33-10VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1018CV33-10VC

Density
1Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
90mA
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05131 Rev. *D
Features
Functional Description
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
Note:
1.
• Pin- and function-compatible with CY7C1018BV33
• High speed
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in Pb-free and non Pb-free 300-mil-wide
Logic Block Diagram
WE
CE
OE
32-pin SOJ
— t
For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
A
A
A
A
A
A
A
A
AA
0
1
2
3
4
5
6
7
8
= 10 ns
INPUT BUFFER
128K x 8
DECODER
ARRAY
COLUMN
[1]
POWER
DOWN
198 Champion Court
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
0
San Jose
through I/O
V
I/O
I/O
V
I/O
I/O
WE
,
128K x 8 Static RAM
CE
CC
A
A
A
A
A
A
A
A
SS
CA 95134-1709
7
0
1
2
0
1
2
3
4
5
6
3
7
Pin Configurations
) is then written into the location
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
Top View
0
SOJ
0
through I/O
Revised August 3, 2006
through A
CY7C1018CV33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
7
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
) are placed in a
).
SS
CC
16
15
14
13
12
11
10
9
8
408-943-2600
7
6
5
4
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CY7C1018CV33-10VC Summary of contents

Page 1

... I/O pins. The eight input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018CV33 is available in a standard 300-mil-wide SOJ. I/O 0 I/O 1 ...

Page 2

... Ind’ MAX , Comm’ – 0.3V, CC Ind’l – 0.3V, CC < 0.3V Test Conditions T = 25° MHz 3.3V CC CY7C1018CV33 -15 Unit Ambient Temperature V CC 3.3V ± 10% 0°C to +70°C 3.3V ± 10% –40°C to +85°C –12 –15 Min. Max. Min. ...

Page 3

... The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t Document #: 38-05131 Rev. *D [4] ALL INPUT PULSES 3.0V 90% 10% GND Rise Time: 1 V/ns [5] -10 Min. Max. Min less than less than t , and t HZCE LZCE HZOE LZOE HZWE HZWE CY7C1018CV33 90% 10% Fall Time: 1 V/ns (b) -12 -15 Max. Min. Max. Unit ...

Page 4

... Data I/O is high impedance 15 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05131 Rev OHA DOE DATA VALID 50 SCE SA t SCE PWE t SD DATA VALID CY7C1018CV33 DATA VALID t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB Page [+] Feedback ...

Page 5

... During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05131 Rev. *D [14, 15 SCE PWE t SD DATA VALID IN [10, 15 SCE PWE t SD DATA VALID Mode 7 Power-down Read Write Selected, Outputs Disabled CY7C1018CV33 LZWE Power Standby ( Active ( Active ( Active ( Page [+] Feedback ...

Page 6

... Ordering Information Speed (ns) Ordering Code 10 CY7C1018CV33-10VC 12 CY7C1018CV33-12VC CY7C1018CV33-12VXI 15 CY7C1018CV33-15VXC Package Diagram All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05131 Rev. *D © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

Page 7

... Document History Page Document Title: CY7C1018CV33 128K x 8 Static RAM Document Number: 38-05131 Issue REV. ECN NO. Date ** 109426 12/14/01 *A 113432 04/10/02 *B 115046 05/30/02 *C 116476 09/16/02 *D 493543 See ECN Document #: 38-05131 Rev. *D Orig. of Change Description of Change HGK New Data Sheet NSL AC Test Loads split based on speed ...

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