CY23S08SC-4 Cypress Semiconductor Corp, CY23S08SC-4 Datasheet

CY23S08SC-4

Manufacturer Part Number

CY23S08SC-4

Description

Manufacturer

Cypress Semiconductor Corp

Type

Zero Delay PLL Clock Bufferr

Datasheet

1.CY23S08SC-4.pdf (10 pages)

Specifications of CY23S08SC-4

Number Of Elements

Operating Supply Voltage (typ)

3.3V

Operating Temp Range

0C to 70C

Package Type

SOIC

Output Frequency Range

15 to 140MHz

Operating Supply Voltage (min)

Operating Supply Voltage (max)

3.6V

Operating Temperature Classification

Commercial

Pin Count

Lead Free Status / Rohs Status

Not Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY23S08SC-4

Manufacturer:

Quantity:

115

Current page: 1 of 10
Download datasheet (387Kb)

Features

■

Functional Description

The CY23S08 is a 3.3V zero delay buffer designed to distribute

high speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

The part has an on-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback must be driven into

the FBK pin, and obtained from one of the outputs. The

input-to-output propagation delay is less than 350 ps, and

output-to-output skew is less than 250 ps.

Cypress Semiconductor Corporation

Document #: 38-07265 Rev. *H

Logic Block Diagram

Zero input output propagation delay, adjustable by capacitive

load on FBK input

Multiple configurations (see Table 3 on page 3)

Multiple low-skew outputs

❐

10 MHz to 140 MHz operating range

65 ps typical cycle-cycle jitter (–1, –1H)

Advanced 0.65μ CMOS technology

Space saving 16-pin, 150-mil SOIC/TSSOP packages

3.3V operation

Spread Aware

45 ps typical output-output skew (–1)

Two banks of four outputs, three-stateable by two select in-

puts

REF

Extra Divider (–3, –4)

•

Extra Divider (–2, –2H, –3)

Select Input

Decoding

198 Champion Court

PLL

MUX

The CY23S08 has two banks of four outputs each, which can be

controlled by the Select inputs as shown in Table 2 on page 3. If

all output clocks are not required, Bank B can be three-stated.

The select inputs also enable the input clock to be directly

applied to the output for chip and system testing purposes.

The CY23S08 PLL enters a power down state when there are no

rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 μA of current draw. The PLL shuts down in two additional

cases as shown in Table 2 on page 3.

Multiple CY23S08 devices accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is less than 700 ps.

The CY23S08 is available in five different configurations, as

shown in Table 3 on page 3. The CY23S08–1 is the base part,

where the output frequencies equal the reference if there is no

counter in the feedback path. The CY23S08–1H is the high drive

version of the –1, and rise and fall times on this device are much

faster.

The CY23S08–2 enables the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the feedback

pin. The CY23S08–2H is the high drive version of the –2, and

rise and fall times on this device are much faster.

The CY23S08–3 enables the user to obtain 4X and 2X

frequencies on the outputs.

The CY23S08–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is versatile, and can be used in a variety

of applications.

•

San Jose

3.3V Zero Delay Buffer

CA 95134-1709

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Revised November 3, 2008

•

CY23S08

408-943-2600

[+] Feedback

Related parts for CY23S08SC-4

CY23S08SC-4 Summary of contents

Page 1

... Logic Block Diagram REF Extra Divider (–3, – Cypress Semiconductor Corporation Document #: 38-07265 Rev. *H The CY23S08 has two banks of four outputs each, which can be controlled by the Select inputs as shown in Table 2 on page 3. If all output clocks are not required, Bank B can be three-stated. ...

Page 2

Pinouts Table 1. Pin Definition - 16-Pin SOIC Package Pin Signal [2] 1 REF [3] 2 CLKA1 [3] 3 CLKA2 GND [3] 6 CLKB1 [3] 7 CLKB2 [ [ [3] 10 CLKB3 ...

Page 3

Table 2. Select Input Decoding S2 S1 CLOCK A1– Three-State 0 1 Driven 1 0 Driven 1 1 Driven Table 3. Available CY23S08 Configurations Device Feedback From CY23S08–1 Bank A or Bank B CY23S08–1H Bank A or Bank ...

Page 4

... IH [7] V Output LOW Voltage OL [7] V Output HIGH Voltage OH I (PD mode) Power down Supply Current REF = 0 MHz DD I Supply Current DD Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices [8] Parameter Name t1 Output Frequency t1 Output Frequency t1 Output Frequency t1 Output Frequency t1 Output Frequency [7] ÷ t Duty Cycle ...

Page 5

... Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices [8] Parameter Name [7] t3 Rise Time (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF [7] t3 Rise Time (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF [7] t3 Rise Time (–1H, -2H) [7] t Fall Time (– ...

Page 6

Switching Waveforms OUTPUT OUTPUT OUTPUT INPUT FBK FBK, Device 1 FBK, Device 2 Document #: 38-07265 Rev. *H Figure 2. Duty Cycle Timing 1.4V 1.4V 1.4V Figure 3. All Outputs Rise and Fall Time 2.0V 2.0V ...

Page 7

Test Circuits 0.1 μF 0.1 μF 0.1 μF 0.1 μF Document #: 38-07265 Rev. *H Figure 7. Test Circuit OUTPUTS V DD GND GND Test Circuit for all parameters except t Figure 8. Test Circuit 2 Test ...

Page 8

... CY23S08SI–2T 16-pin 150-mil SOIC–Tape and Reel CY23S08SC–2H 16-pin 150-mil SOIC CY23S08SC–2HT 16-pin 150-mil SOIC–Tape and Reel CY23S08SC–3 16-pin 150-mil SOIC CY23S08SC–3T 16-pin 150-mil SOIC–Tape and Reel CY23S08SC–4 16-pin 150-mil SOIC CY23S08SC–4T 16-pin 150-mil SOIC– ...

Page 9

Package Drawings and Dimensions 8 9 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Figure 10. 16-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z16 1 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document #: ...

Page 10

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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