CY7C342B-25HC Cypress Semiconductor Corp, CY7C342B-25HC Datasheet - Page 3

• Manufacturer Part Number: CY7C342B-25HC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C342B-25HC

• Family Name: MAX®
• Memory Type: EPROM
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 62.5MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 52
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: Windowed LCC
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03014 Rev. *B
Logic Array Blocks
There are eight logic array blocks in the CY7C342B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
Externally, the CY7C342B provides eight dedicated inputs,
one of which may be used as a system clock. There are 52 I/O
pins that may be individually configured for input, output, or
bidirectional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals that may
cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or
races are avoided. The result is ease of design implemen-
tation, often in a signal pass, without the multiple internal logic
INPUT
DELAY
INPUT
DELAY
PIA
t
t
PIA
IN
SYSTEM CLOCK DELAY t
Figure 1. CY7C342B Internal Timing Model
USE ULTRA37000
CONTROL DELAY
LOGIC ARRAY
LOGIC ARRAY
EXPANDER
ALL NEW DESIGNS
DELAY
DELAY
CLOCK
DELAY
t
t
t
EXP
LAD
LAC
I/O DELAY
t
IC
t
IO
t
t
t
t
CLR
PRE
RSU
RH
ICS
FEEDBACK
placement and routing iterations required for a programmable
gate array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C342B may be easily determined
using Warp
software by the model shown in Figure 1. The CY7C342B has
fixed internal delays, allowing the user to determine the
worst-case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this datasheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C342B contains circuitry to protect
device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND < (V
inputs must always be tied to an appropriate logic level
(either V
be connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between V
each V
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
DELAY
t
FD
TM
REGISTER
CC
CC
t
t
LATCH
COMB
FOR
t
CC
RD
®
pin should be separately decoupled to GND
or GND). Each set of V
, Warp Professional™, or Warp Enterprise™
and GND. For the most effective decoupling,
OUTPUT
DELAY
t
t
t
OD
XZ
ZX
IN
or V
CC
and GND pins must
OUT
CY7C342B
) < V
OUTPUT
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