CY7C1360A-200BGC Cypress Semiconductor Corp, CY7C1360A-200BGC Datasheet - Page 5

• Manufacturer Part Number: CY7C1360A-200BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1360A-200BGC

• Density: 9Mb
• Access Time (max): 3ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Supply Current: 510mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05258 Rev. *A
256K × 36 Pin Descriptions
4P
4N
2A, 3A, 5A, 6A, 3B, 5B,
6B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
5L
5G
3G
3L
4M
4H
4K
4E
2B
–
(not available for
PBGA)
4F
4G
4A
4B
3R
7T
X36 PBGA Pins
37
36
35, 34, 33, 32, 100,
99, 82, 81, 44, 45,
46, 47, 48, 49, 50
92 (T/AJ Version)
43 (TA/A Version)
93
94
95
96
87
88
89
98
97
92
(for TA/A version
only)
86
83
84
85
31
64
X36 QFP Pins
A0
A1
A
BWa
BWb
BWc
BWd
BWE
GW
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
MODE
ZZ
Name
2
3
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Type
Input
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
Byte Write: A byte Write is LOW for a Write cycle and
HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, condi-
tioned by BWE being LOW.
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit
Write to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the rising
edge of CLK.
Clock: This signal registers the addresses, data, chip
enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Chip Enable: This active HIGH input is used to enable
the device.
Chip Enable: This active LOW input is used to enable the
device. Not available for B and T package versions.
Output Enable: This active LOW asynchronous input
enables the data output drivers.
Address Advance: This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
Address Status Processor: This active LOW input,
along with CE being LOW, causes a new external address
to be registered and a Read cycle is initiated using the
new address.
Address Status Controller: This active LOW input
causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Sleep: This active HIGH input puts the device in low
power consumption standby mode. For normal operation,
this input has to be either LOW or NC (No Connect).
Description
CY7C1360A
CY7C1362A
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