CY7C09359A-7AC Cypress Semiconductor Corp, CY7C09359A-7AC Datasheet
CY7C09359A-7AC
Specifications of CY7C09359A-7AC
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CY7C09359A-7AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09349A) — organization (CY7C09359A) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • ...
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... Functional Description The CY7C09349A and CY7C09359A are high-speed synchro- nous CMOS 4K and dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time ...
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... SB1 (Both Ports TTL Level) Typical Standby Current for I (mA) SB3 (Both Ports CMOS Level) Note: 4. This pin is NC for CY7C09349A. Document #: 38-06048 Rev. ** 100-Pin TQFP (Top View CY7C09359A (8K x 18) CY7C09349A ( CY7C09349A CY7C09349A CY7C09359A CY7C09359A [1] -6 100 6.5 250 45 ...
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... Ambient Temperature with Power Applied ..– +125 C Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Note: 5. Industrial Parts are available in CY7C09359A only. Document #: 38-06048 Rev. ** Description –A for 4K, A –A for 8K devices). ...
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... Com’l. 0.05 0.5 0.05 [5] Ind. Com’l. 160 200 145 [5] Ind. Description Test Conditions MHz 5.0V CC AND CE 0 CY7C09349A CY7C09359A CY7C09349A CY7C09359A -9 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 10 –10 10 –10 420 215 360 195 240 410 105 110 ...
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... Note: 7. Test Conditions pF. Document #: 38-06048 Rev 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) [7] 3.0V GND = 1. Capacitance (pF) (b) Load Derating Curve CY7C09349A CY7C09359A 5V OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for CKLZ OLZ including scope and jig) ALL INPUT PULSES 90% 90% 10% 10 ...
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... Clock to Clock Set-up Time CCS Note: 8. Test conditions used are Load 2. Document #: 38-06048 Rev. ** CY7C09349A CY7C09359A [ Min. Max. Min. Max. Min 100 6.5 7.5 12 6 6.5 7 CY7C09349A CY7C09359A -12 Max. Min. Max. Unit 40 33 MHz 67 50 MHz Page ...
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... Q n [9, 10, 11, 12 CYC2 t CL2 A A n+1 t CD2 Q t CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09349A CY7C09359A n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ n+2 ...
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... CD2 HC CD2 [15, 16, 17, 18 MATCH CD1 CWDD , R/W, CNTEN, and CNTRST = for the left port, which is being written to. IH CY7C09349A CY7C09359A CD2 CKHZ CKLZ CD2 CKHZ CKLZ NO NO MATCH t CD1 VALID >maximum specified, then data is not valid CWDD CCS CKHZ CD2 ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06048 Rev. ** [12, 19, 20, 21 n+1 n CD2 CKHZ Q n READ NO OPERATION [12, 19, 20, 21 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09349A CY7C09359A A A n+3 n CKLZ WRITE READ A A n+4 n CKLZ CD2 READ Page CD2 Q n+3 Q n+4 ...
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... OUT OE Document #: 38-06048 Rev. ** [10, 12, 19, 20 n+1 n CD1 CKHZ NO READ OPERATION [10, 12, 19, 20 n OHZ READ CY7C09349A CY7C09359A n+2 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n CD1 CKLZ DC WRITE READ A n+4 t CD1 A n+5 t CD1 n+4 Page ...
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... R/W and CNTRST = Document #: 38-06048 Rev. ** [22] t SAD t SCN t CD2 READ WITH COUNTER [22 n+1 READ WITH COUNTER . IH CY7C09349A CY7C09359A t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+2 READ COUNTER HOLD WITH COUNTER Q n+3 Q n+3 Page ...
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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06048 Rev n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09349A CY7C09359A [23, 24 n+2 n n+2 n+3 n+4 WRITE WITH COUNTER . IH A n+4 Page ...
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... SD DATA IN DATA OUT COUNTER RESET Notes: 25 UB, and 26. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06048 Rev. ** [12, 19, 25, 26 WRITE READ ADDRESS 0 ADDRESS 0 CY7C09349A CY7C09359A n READ READ ADDRESS 1 ADDRESS n Page n ...
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... CNTRST I/O Mode Reset out( out( out( Increment out(n+ CY7C09349A CY7C09359A Operation 17 [30] Deselected [30] Deselected Write IN [30] Read Outputs Disabled Operation Counter Reset to Address 0 Load Address Load into Counter Hold External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page ...
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... CY7C09349A-12AC 8K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09359A-6AC 7.5 CY7C09359A-7AC 9 CY7C09359A-9AC CY7C09359A-9AI 12 CY7C09359A-12AC Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06048 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
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... Document Title: CY7C09349A/CY7C09359A 4K/ Synchronous Dual-Port Static RAM Document Number: 38-06048 Issue REV. ECN NO. Date ** 110200 09/29/01 Document #: 38-06048 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00834 to 38-06048 CY7C09349A CY7C09359A Page ...