LH28F640SPHT-PTL12A Sharp Electronics, LH28F640SPHT-PTL12A Datasheet - Page 7

• Manufacturer Part Number: LH28F640SPHT-PTL12A
• Manufacturer: Sharp Electronics

Specifications of LH28F640SPHT-PTL12A

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

DQ
Symbol
BYTE#
A
V
V
GND
WE#
CE
CE
OE#
RP#
STS
V
CE
22
15
NC
A
CCQ
PEN
CC
-A
-DQ
0
0
1
2
,
,
1
0
OPEN DRAIN
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Lowest address input in byte mode (BYTE#=V
Address is internally latched during an erase or a program cycle. This pin is not used in
word mode (BYTE#=V
ADDRESS INPUTS: Inputs for addresses during read, erase and program operations.
Addresses are internally latched during an erase or a program cycle.
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code reads. Data pins float to high-impedance (High Z) when the chip or
outputs are deselected. Data is internally latched during an erase or program cycle.
DQ
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. When the device is de-selected, power consumption reduces to standby
levels. Refer to Table 2 to determine whether the device is selected or de-selected
depending on the state of CE
RESET: When low (V
operations, which provides data protection. RP#-high (V
After power-up or reset mode, the device is automatically set to read array mode.
RP# must be low during power-up/down.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the first edge of CE
WE# (whichever occurs first).
STATUS: Indicates the status of the internal WSM (Write State Machine). When
configured in level mode (default mode), STS acts as a RY/BY# pin (STS is V
the WSM is executing internal erase or program algorithms). When configured in one of
its pulse modes, STS can pulse to indicate erase/program completion. Refer to Table 9
for STS configuration.
BYTE ENABLE: BYTE# V
DQ
device in word mode (×16) and A
MONITORING POWER SUPPLY VOLTAGE: V
With V
OTP program cannot be executed and should not be attempted.
DEVICE POWER SUPPLY (2.7V-3.6V): With V
flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted.
INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output
pins.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
15
8
-DQ
is floated (High Z) and A
PEN
8
≤V
pins are not used in byte mode (BYTE#=V
Table 1. Pin Descriptions
PENLK
LHF64P05
, block erase, (page buffer) program, block lock configuration and
IL
IH
), RP# resets internal automation and inhibits erase and program
: ×16 bit)
IL
0
, CE
0
places the device in byte mode (×8). In this mode, DQ
, CE
0
1
Name and Function
1
is the lowest address input. BYTE# V
is the lowest address input.
1
and CE
or CE
2
2
.
that disables the device or the rising edge of
PEN
CC
≤V
IL
is not used for power supply pin.
: ×8 bit).
LKO
IH
) enables normal operation.
, all write attempts to the
CC
voltage (refer to DC
IH
IL
Rev. 0.06
places the
: ×8 bit).
OL
when
4
15
-