LH28F160BJHE-BTLZD Sharp Electronics, LH28F160BJHE-BTLZD Datasheet - Page 15

• Manufacturer Part Number: LH28F160BJHE-BTLZD
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTLZD

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V
this high voltage, block contents are protected against
erasure. If block erase is attempted while V
SR.3 and SR.5 will be set to "1". Successful block erase
requires for boot blocks that WP# is V
corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleared the corresponding
block lock-bit. If block erase is attempted when the
excepting above conditions, SR.1 and SR.5 will be set to
"1".
4.6 Full Chip Erase Command
This command followed by a confirm command erases all
of the unlocked blocks. A full chip erase setup (30H) is
first written, followed by a full chip erase confirm (D0H).
After a confirm command is written, device erases the all
unlocked blocks block by block. This command sequence
requires appropriate sequencing. Block preconditioning,
erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip
erase sequence is written, the device automatically outputs
status register data when read (see Figure 6). The CPU can
detect full chip erase completion by analyzing the output
data of the status register bit SR.7.
When the full chip erase is complete, status register bit
SR.5 should be checked. If erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
CC
=2.7V-3.6V and V
CCW
=V
CCWH1/2
. In the absence of
CCW
IH
V
and the
CCWLK
,
status register mode until a new command is issued. If
error is detected on a block during full chip erase
operation, WSM stops erasing. Full chip erase operation
start from lower address block, finish the higher address
block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequence
will result in both status register bits SR.4 and SR.5 being
set to "1". Also, reliable full chip erasure can only occur
when V
absence of this high voltage, block contents are protected
against erasure. If full chip erase is attempted while
V
Successful full chip erase requires for boot blocks that
WP# is V
cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If all blocks are
locked, SR.1 and SR.5 will be set to "1".
4.7 Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or alternate
10H) is written, followed by a second write that specifies
the address and data (latched on the rising edge of WE#).
The WSM then takes over, controlling the word write and
write verify algorithms internally. After the word write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The CPU can
detect the completion of the word write event by analyzing
the status register bit SR.7.
When word write is complete, status register bit SR.4
should be checked. If word write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable
V
this high voltage, memory contents are protected against
word
V
set to "1". Successful word write requires for boot blocks
that WP# is V
cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If word write is
attempted when the excepting above conditions, SR.1 and
SR.4 will be set to "1".
CCW
CC
CCW
=2.7V-3.6V and V
V
V
writes. If word write is attempted while
CC
CCWLK
CCWLK
IH
=2.7V-3.6V and V
word
IH
and the corresponding block lock-bit be
, SR.3 and SR.5 will be set to "1".
, status register bits SR.3 and SR.4 will be
and the corresponding block lock-bit be
writes
CCW
=V
can
CCWH1/2
CCW
only
=V
. In the absence of
CCWH1/2
occur
. In the
Rev. 1.27
when