LH28F008SAN-85 Sharp Electronics, LH28F008SAN-85 Datasheet
LH28F008SAN-85
Specifications of LH28F008SAN-85
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LH28F008SAN-85 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F008SAN-85 Flash Memory (Model No.: LHF08SZM) Issue Date: February 13, 2003 ® 8M (1MB × 8) Spec No.: EL1S2040 Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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FEATURES 2 PRODUCT OVERVIEW 3 PRINCIPLES OF OPERATION 4 BUS OPERATION 5 COMMAND DEFINITIONS 6 EXTENDED BLOCK ERASE/BYTE WRITE CYCLING ························ 7 AUTOMATED BYTE WRITE 8 AUTOMATED BLOCK ERASE 9 DESIGN CONSIDERATIONS 10 ABSOLUTE MAXIMUM RATINGS 11 OPERATING ...
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... Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high density data acquisition applications, the LH28F008SAN-85 offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of the LH28F008SA’ ...
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... Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the LH28F008SAN-85. The LH28F008SAN-85 is available in the 44-lead PSOP (Plastic Small Outline Package) package. Pinout is shown in Figure 2 of this specification. The Command User Interface serves as the interface be- tween the microprocessor or microcontroller and the inter- nal operation of the LH28F008SAN-85 ...
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MULTIPLEXER LHF08SZM REGISTER DATA OUTPUT Figure 1. Block Diagram 4 ...
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Symbol Type ADDRESS INPUTS: for memory addresses. Addresses are internally A -A INPUT 0 19 latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during Command User Interface write cycles; outputs data during memory array, Status DQ ...
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RP ...
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0- 21-22 17-20 LATCH SBHE# SBHE# PSTART# PCMD# 80386SL 80386SL µPLD PM/IO# PW/R# FLSHDCS# PRDY# VGACS# CTRL SD 0-15 XCVR INT RY/BY# 82360SL # RESET Controller POWERGOOD EPLD(s) Figure 3. LH28F008SA Array ...
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... Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the LH28F008SAN-85 blocks. This code is copied to, and ex- ecuted from, system RAM during actual flash memory up- date. After successful completion of byte write and/or block erase, code/data reads from the LH28F008SAN-85 are again possible via the Read Array command ...
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... Status Register). The LH28F008SAN-85 auto- matically resets to Read Array mode upon initial device powerup or after exit from deep powerdown. The LH28F008SAN-85 has four control pins, two of which must be logically active to obtain data at the outputs. Chip Enable (CE#) is the device selection control, and when active en- ables the selected memory device ...
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... Deep Power-Down The LH28F008SAN-85 offers a deep powerdown feature, entered when RP Current draw thru V IL maximum in deep powerdown mode, with current draw through V maximal 5µA. During read modes, RP#-low PP deselects the memory, places output drivers in a high- impedence state and turns off all internal circuits. The ...
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... V PP PPL Intelligent Identifier Command The LH28F008SAN-85 contains an intelligent identifier op- eration, initiated by writing 90H into the Command User In- terface. Following the command write, a read cycle from ad- dress 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H ...
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... The Erase Suspend Status and WSM Status bits of the Status Register will be automatically cleared and RY/BY# will return to V sume command is written to it, the LH28F008SAN-85 auto- matically outputs Status Register data when read (see Fig- ure 7; Erase Suspend/Resume Flowchart). V ...
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... DESIGN CONSIDERATIONS Three-Line Output Control The LH28F008SAN-85 will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a) lowest possible memory power dissipation ...
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... Byte Write Successful Figure 5. Automated Byte Write Flowchart LHF08SZM RY/BY# can be connected to the interrupt input of the sys- tem CPU or controller active at all times, not tristated if the LH28F008SAN-85 CE# or OE# inputs are brought RY/BY# is also V when the device is in Erase Sus pend or deep powerdown modes. ...
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Start Write 20H, Block Address Write D0H Block Address NO Erase Suspend WSM NO Suspend Ready? Erase? YES YES Full Status Check if Desired Block Erase Completed FULL STATUS CHECK PROCEDURE Status Register Data Read (See Above) V Range ...
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... SB V Trace on Printed Circuit Boards PP Writing flash memories, while they reside in the target sys- tem, requires that the printed circuit board designer pay at- tention to the V power supply trace. The V PP the memory cell current for writing and erasing. Use similar and GND ...
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... Flash nonvolatility increases usable battery life, because the LH28F008SAN-85 does not consume any power to re- or CE# PP tain code or data when the system is off. ...
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ABSOLUTE MAXIMUM RATINGS* Operating Temperature During Read .........................................0˚C to +70˚C During Block Erase/Byte Write ................0˚C to +70˚C Temperature Under Bias .....................-10˚C to +80˚C Storage Temperature ........................-65˚C to +125˚C Voltage on Any Pin (except V and ...
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DC CHARACTERISTICS (Continued) Symbol Parameter I V Byte Write Current CCW Block Erase Current CCE Erase Suspend Current CCES Standby Current PPS Deep PowerDown PPD PP Current ...
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AC INPUT/OUTPUT REFERENCE WAVEFORM (1) 2.4 2.0 INPUT TEST POINTS 0.8 0.45 AC test inputs are driven at V (2.4V OH TTL (0.45V ) for a Logic "0". Input timing begins at V TTL (0.8V ). Output timing ends ...
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Figure 8. AC Waveform for Read Operations LHF08SZM 21 ...
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... IN 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard SHARP flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measure to completion (SR.7=1, RY/ BY#=V nation of byte write/block erase success (SR ...
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BLOCK ERASE AND BYTE WRITE PERFORMANCE Parameter Notes Block Erase Time Block Write Time Byte Write Time NOTES =+25˚C, 12. Excludes System-Level Overhead. AC CHARACTERISTICS - Reset Operation V OH RY/BY#(R) ...
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Figure 9. AC Waveform for Write Operations 24 ...
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ALTERNATIVE CE#-CONTROLLED WRITES Versions Symbol Parameter t t Write Cycle Time AVAV RP# High Recovery to PHEL PS CE# Going Low t t WE# Setup to CE# Going WLEL WS Low t t CE# Pulse Width ...
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Figure 10. AC Waveform for Write Operations 26 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...