LH28F008SCN-V85 Sharp Electronics, LH28F008SCN-V85 Datasheet - Page 28

• Manufacturer Part Number: LH28F008SCN-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCN-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

6.2.3 DC CHARACTERISTICS (contd.)
NOTES :
1. All currents are in RMS unless otherwise noted. Typical
2. I
3. Includes RY/BY#.
4. Block erases, byte writes, and lock-bit configurations are
5. Automatic Power Saving (APS) reduces typical I
SYMBOL
V
V
V
V
V
V
V
V
V
V
IL
IH
OL
OH1
OH2
PPLK
PPH1
PPH2
LKO
HH
values at nominal V
currents are valid for all product versions (packages and
speeds).
selected. If reading or byte writing in erase suspend
mode, the device’s current draw is the sum of I
I
inhibited when V
range between V
V
1 mA at 5 V V
CCWS
CCES
PPH1
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
V
Normal Operations
V
Block Erase or Lock-Bit Operations
V
Block Erase or Lock-Bit Operations
V
RP# Unlock Voltage
and I
(max.) and V
PP
PP
PP
CC
and I
Lockout Voltage during
Voltage during Byte Write,
Voltage during Byte Write,
Lockout Voltage
CCR
CCES
CC
or I
PP
PPLK
PARAMETER
in static operation.
CCW
PPH2
are specified with the device de-
≤ V
CC
(max.) and V
, respectively.
PPLK
voltage and T
(min.), and above V
, and not guaranteed in the
PPH1
A
= +25˚C. These
(min.), between
PPH2
NOTE
CCWS
3, 7
3, 7
3, 7
4, 7
8, 9
(max.).
7
7
CCR
or
to
- 28 -
– 0.5
– 0.4
0.85
11.4
11.4
V
MIN.
V
V
2.0
2.4
4.5
2.0
CC
CC
CC
6. CMOS inputs are either V
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# =
9. RP# connection to a V
= 5.0±0.5 V
inputs are either V
V
when the master lock-bit is set and RP# = V
erases and byte writes are inhibited when the
corresponding block lock-bit is set and RP# = V
erase, byte write, and lock-bit configuration operations
are not guaranteed with V
be attempted.
maximum cumulative period of 80 hours.
IH
. Block lock-bit configuration operations are inhibited
MAX.
+0.5
0.45
12.6
12.6
V
0.8
1.5
5.5
CC
UNIT
V
V
V
V
V
V
V
V
V
V
V
IL
V
I
V
I
V
I
V
I
Set master lock-bit
Override master and
block lock-bit
or V
OL
OH
OH
OH
CC
CC
CC
CC
= 5.8 mA
= –2.5 mA
= –2.5 mA
= –100 µA
IH
LH28F008SC-V/SCH-V
= V
= V
= V
= V
IH <
CC
HH
.
±0.2 V or GND±0.2 V. TTL
CC
CC
CC
CC
RP# < V
supply is allowed for a
CONDITIONS
Min.
Min.
Min.
Min.
TEST
HH
and should not
IH
IH
. Block
. Block