AT49BV8192-15TC Atmel, AT49BV8192-15TC Datasheet - Page 5

• Manufacturer Part Number: AT49BV8192-15TC
• Manufacturer: Atmel

Specifications of AT49BV8192-15TC

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

Command Definition (in Hex)
Notes:
Absolute Maximum Ratings*
Command
Sequence
Read
Chip Erase
Sector Erase
Word Program
Boot Block Lockout
Product ID Entry
Product ID Exit
Product ID Exit
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
Voltage on RESET
with Respect to Ground ...................................-0.6V to +13.5V
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
2. The 8K word boot sector has the address range 00000H to 01FFFH for the AT49BV/LV8192 and 7E000H to 7FFFFH for the
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
AT49BV/LV8192T.
For the AT49BV/LV8192
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 7FXXX for MAIN MEMORY ARRAY
For the AT49BV/LV8192T
SA = 7DXXX for PARAMETER BLOCK 1
SA = 7BXXX for PARAMETER BLOCK 2
SA = 79XXX for MAIN MEMORY ARRAY
together (form the same sector erase command). Once the boot region has been protected, only the main memory array
sector will erase when its sector erase command is issued.
(3)
(3)
(2)
Cycles
Bus
1
6
6
4
6
3
3
1
Addr
Addr
5555
5555
5555
5555
5555
5555
xxxx
1st Bus
Cycle
Data
D
AA
AA
AA
AA
AA
AA
F0
OUT
(1)
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
Addr
CC
2nd Bus
+ 0.6V
Cycle
Data
55
55
55
55
55
55
Addr
5555
5555
5555
5555
5555
5555
*NOTICE:
3rd Bus
Cycle
Data
A0
F0
80
80
80
90
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Stresses beyond those listed under “Absolute
Addr
5555
5555
5555
Addr
4th Bus
Cycle
Data
D
AA
AA
AA
IN
2AAA
2AAA
2AAA
Addr
5th Bus
Cycle
Data
55
55
55
SA
Addr
5555
5555
(4)(5)
6th Bus
Cycle
Data
30
10
40
5