IS61C256AH-12T ISSI, Integrated Silicon Solution Inc, IS61C256AH-12T Datasheet
IS61C256AH-12T
Specifications of IS61C256AH-12T
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IS61C256AH-12T Summary of contents
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... LOW Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C256AH is pin compatible with other 32K x 8 SRAMs and are available in 28-pin SOJ and TSOP (Type I) packages. DECODER ...
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... IS61C256AH PIN CONFIGURATION 28-Pin SOJ A14 1 28 VCC A12 A13 A11 A10 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports Vcc Power GND Ground ABSOLUTE MAXIMUM RATINGS ...
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... IS61C256AH OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage ( Input Leakage LI I Output Leakage LO Note –3.0V for pulse width less than 10 ns. ...
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... IS61C256AH CAPACITANCE (1,2) Symbol Parameter C Input Capacitance IN C Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz, Vcc = 5.0V. A READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time ...
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... IS61C256AH AC TEST LOADS 480 Ω 5V OUTPUT 30 pF Including jig and scope Figure 1 AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID (1,3) READ CYCLE NO. 2 ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions. ...
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... IS61C256AH WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold HA from Write End t Address Setup Time SA WE Pulse Width (OE LOW PWE WE Pulse Width (OE HIGH PWE t Data Setup to Write End SD t Data Hold from Write End ...
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... IS61C256AH WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ADDRESS OE LOW CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...
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... IS61C256AH-12TL 15 IS61C256AH-15J IS61C256AH-15JL IS61C256AH-15T 20 IS61C256AH-20J IS61C256AH-20T ORDERING INFORMATION: IS61C256AH Industrial Range: –40°C to +85°C Speed (ns) Order Part Number 12 IS61C256AH-12JI IS61C256AH-12TI 15 IS61C256AH-15JI IS61C256AH-15TI 20 IS61C256AH-20JI IS61C256AH-20TI 8 Package 300-mil Plastic SOJ TSOP (Type 1) 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free TSOP (Type 1) TSOP (Type 1), Lead-free ...
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... IS61C256AH Integrated Silicon Solution, Inc. — www.issi.com — Rev. S 08/24/09 1-800-379-4774 9 ...
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... IS61C256AH 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. S 08/24/09 ...