IDT74LVC16823APV IDT, Integrated Device Technology Inc, IDT74LVC16823APV Datasheet

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IDT74LVC16823APV

Manufacturer Part Number
IDT74LVC16823APV
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Dr
Datasheet

Specifications of IDT74LVC16823APV

Logic Family
LVC
Technology
CMOS
Number Of Bits
18
Number Of Elements
2
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
3.3V
Package Type
SSOP
Propagation Delay Time
8.9ns
Output Type
3-State
Low Level Output Current
24mA
High Level Output Current
-24mA
Frequency (max)
150MHz
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
FEATURES:
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2006 Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16823A
3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS
1
machine model (C = 200pF, R = 0)
CLKEN
1
1
CC
CC
CLK
1
CLR
OE
1
= 3.3V ± 0.3V, Normal Range
= 2.7V to 3.6V, Extended Range
D
1
54
2
1
56
55
SK(o)
(Output Skew) < 250ps
TO EIGHT OTHER CHANNELS
3.3V CMOS
18-BIT REGISTER
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
R
C
D
R
C
D
3
1
Q
2
CLKEN
1
1
2
2
CLK
2
CLR
DESCRIPTION:
technology. This high-speed, low-power register is ideal for use as a buffer
register for data synchronization and storage. The Output Enable (OE) and
clock (CLK) controls are organized to operate each device as two 9-bit
registers or one 18-bit register with common clock. Flow-through organi-
zation of signal pins simplifies layout. All inputs are designed with hysteresis
for improved noise margin.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
OE
2
The LVC16823A 18-bit register is built using advanced dual metal CMOS
All pins of the LVC16823A can be driven from either 3.3V or 5V devices.
The LVC16823A has been designed with a
D
1
29
30
27
28
42
TO EIGHT OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16823A
R
C
D
R
C
D
±
24mA output driver. The
February 20, 2009
DSC-4573/6
15
2
Q
1

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IDT74LVC16823APV Summary of contents

Page 1

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS FEATURES: • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF • 3.3V ...

Page 2

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS PIN CONFIGURATION CLR GND ...

Page 3

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage ...

Page 4

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS OPERATING CHARACTERISTICS, V Symbol Parameter C Power Dissipation Capacitance per Flip-Flop Outputs enabled PD C Power Dissipation Capacitance per Flip-Flop Outputs disabled PD SWITCHING CHARACTERISTICS Symbol Parameter f MAX t Propagation Delay ...

Page 5

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 ...

Page 6

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS ORDERING INFORMATION LVC Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXXX Device Type Package PV PVG PA PAG 823A 16 ...

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