IR2520D International Rectifier, IR2520D Datasheet - Page 7

IR2520D

Manufacturer Part Number
IR2520D
Description
Manufacturer
International Rectifier
Datasheet

Specifications of IR2520D

Operating Temperature (max)
125C
Operating Temperature (min)
-25C
Pin Count
8
Mounting
Through Hole
Package Type
PDIP
Screening Level
Commercial
Lead Free Status / Rohs Status
Not Compliant

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Functional Description
Under-voltage Lock-Out Mode
The under-voltage lock-out mode (UVLO) is defined as the
state the IR2520D is in when VCC is below the turn-on
threshold of the IC. The IR2520D UVLO is designed to main-
tain an ultra-low supply current (I
guarantee that the IR2520D is fully functional before the
high- and low-side output gate drivers are activated. The
VCC capacitor, CVCC, is charged by current through sup-
ply resistor, RSUPPLY, minus the start-up current drawn by
the IR2520D (Figure 1). This resistor is chosen to provide
sufficient current to supply the IR2520D from the DC bus.
Once the capacitor voltage on VCC reaches the start-up
threshold, V
start oscillating. Capacitor CVCC should be large enough to
hold the voltage at VCC above the V
one half-cycle of the line voltage or until the external auxil-
iary supply can maintain the required supply voltage and
current to the IC.
An internal bootstrap MOSFET between VCC and VB and
external supply capacitor, CBS, determine the supply volt-
age for the high-side driver circuitry. An external charge
pump circuit consisting of capacitor CSNUB and diodes DCP1
and DCP2, comprises the auxiliary supply voltage for the
low-side driver circuitry. To guarantee that the high-side
supply is charged up before the first pulse on pin HO, the
first pulse from the output drivers comes from the LO pin.
LO may oscillate several times until VB-VS exceeds the
high-side UVLO rising threshold, V
DCBUS(+)
DCBUS(-)
RSUPPLY
CVCC
RFMIN
CVCO
CCUV
COM
FMIN
VCC
VCO
Fig. 1 Start-up circuitry
1
2
3
4
+ , the IR2520D turns on and HO and LO
CLAMP
15.6V
Bootstrap
UVLO
Driver
VCC
FET
Driver
High-
Low-
and
side
DCP2
8
7
6
5
VB
HO
VS
LO
BSUV+
QCCUV
CBS
MHS
MLS
CCUV
(9 Volts), and the
<80uA), and to
CSNUB
DCP1
+ threshold for
TO LOAD
LOAD RETURN
high-side driver is enabled. During UVLO mode, the high- and
low-side gate driver outputs, HO and LO, are both low and
pin VCO is pulled down to COM for resetting the starting
frequency to the maximum.
Frequency Sweep Mode
When VCC exceeds V
frequency sweep mode. An internal current source (Figure
2) charges the external capacitor on pin VCO, CVCO, and
the voltage on pin VCO starts ramping up linearly. An addi-
tional quick-start current (I
VCO pin and charges the VCO pin initially to 0.85V. When the
VCO voltage exceeds 0.85V, the quick-start current is then
disconnected internally and the VCO voltage continues to
charge up with the normal frequency sweep current source
(I
quickly to the internal range of the VCO. The frequency ramps
down towards the resonance frequency of the high-Q bal-
last output stage causing the lamp voltage and load current to
increase. The voltage on pin VCO continues to increase and
the frequency keeps decreasing until the lamp ignites. If the
lamp ignites successfully, the voltage on pin VCO continues
to increase until it internally limits at 6V (V
frequency stops decreasing and stays at the minimum fre-
quency as programmed by an external resistor, RFMIN, on
pin FMIN. The minimum frequency should be set below the
high-Q resonance frequency of the ballast output stage to
ensure that the frequency ramps through resonance for lamp
ignition (Figure 4). The desired preheat time can be set by
adjusting the slope of the VCO ramp with the external capaci-
tor CVCO.
VCOFS
Fig. 2 Frequency sweep circuitry mode circuitry
DCBUS(+)
DCBUS(-)
) (Figure 3). This quick-start brings the VCO voltage
RSUPPLY
CVCC
RFMIN
CVCO
IR2520D(S) & (PbF)
VCC
COM
FMIN
VCO
1
2
3
4
CLAMP
15.6V
CCUV
Bootstrap
VCO
Driver
FET
VCOQS
+ threshold, the IR2520D enters
Driver
High-
Low-
and
side
DCP2
8
7
6
5
) is also connected to the
VB
HO
VS
LO
CBS
MHS
MLS
VCO_MAX
CSNUB
DCP1
TO LOAD
LOAD RETURN
). The
7

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