LSM303DLM STMicroelectronics, LSM303DLM Datasheet - Page 23

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LSM303DLM

Manufacturer Part Number
LSM303DLM
Description
Board Mount Accelerometers 3axis accelerometr & 3-axis magnetometer
Manufacturer
STMicroelectronics
Datasheet

Specifications of LSM303DLM

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LSM303DLM
9
9.1
9.1.1
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The register address, made up of 7 bits, is used to identify them and to
write the data through the serial interface.
Linear acceleration register description
CTRL_REG1_A (20h)
Table 16.
Table 17.
PM bits allow selection between power-down and two operating active modes. The device is
in power-down mode when the PD bits are set to “000” (default value after boot).
shows all the possible power mode configurations and respective output data rates. Output
data in the low-power modes are computed with a low-pass filter cut-off frequency defined
by DR1 and DR0 bits.
DR bits, in normal-mode operation, select the data rate at which acceleration samples are
produced. In low-power mode they define the output data resolution.
possible configurations for the DR1 and DR0 bits.
Table 18.
PM2 - PM0
DR1, DR0
Zen
Yen
Xen
PM2
PM2
0
0
0
CTRL_REG1_A register
CTRL_REG1_A description
Power mode and low-power output data rate configurations
PM1
PM1
Power mode selection. Default value: 000
(000: power-down; others: refer to
Data rate selection. Default value: 00
(00:50 Hz; others: refer to
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
0
0
1
PM0
PM0
0
1
0
Doc ID 018725 Rev 1
DR1
Power mode selection
Table
Normal mode
Power-down
Low-power
19)
Table
DR0
18)
Zen
Output data rate [Hz]
Table 19
Register description
Yen
ODR
ODR
0.5
--
shows all the
LP
Table 18
Xen
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