LFXP2-5E-5MN132C Lattice, LFXP2-5E-5MN132C Datasheet - Page 16

• Manufacturer Part Number: LFXP2-5E-5MN132C
• Description: IC FPGA 5KLUTS 86I/O 132-BGA
• Manufacturer: Lattice

Specifications of LFXP2-5E-5MN132C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1248

Lattice Semiconductor
LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have
eight secondary clocks (SC0 to SC7) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for high fan-out control and SC4 to SC7 are used
for clock signals.
Figure 2-11. Secondary Clock Regions XP2-40
Figure 2-12. Secondary Clock Selection
SC0
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
4:1
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
Region 4
SC1
4:1
Secondary Clock Sources: 8 PIOs + 16 Routing
SC2
4:1
8 Secondary Clocks (SC0 to SC7)
SC3
4:1
Clock/Control
2-13
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
SC4
Region 5
I/O Bank 1
Region 6
Region 7
Region 8
I/O Bank 4
4:1
SC5
4:1
SC6
LatticeXP2 Family Data Sheet
4:1
SC7
4:1
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
Architecture