DP83848IVV National Semiconductor, DP83848IVV Datasheet - Page 23

no-image

DP83848IVV

Manufacturer Part Number
DP83848IVV
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83848IVV

Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DP83848IVV
Manufacturer:
NSC
Quantity:
6
Part Number:
DP83848IVV
Manufacturer:
TI/德州仪器
Quantity:
20 000
Part Number:
DP83848IVV/NOPB
Manufacturer:
TI
Quantity:
17 200
Part Number:
DP83848IVV/NOPB
Manufacturer:
NS
Quantity:
6 125
Part Number:
DP83848IVV/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83848IVV/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
Part Number:
DP83848IVV/NOPB
0
Part Number:
DP83848IVVX
0
Part Number:
DP83848IVVX/NOPB
Manufacturer:
CYPRESS
Quantity:
1 560
Part Number:
DP83848IVVX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83848IVVX/NOPB
Manufacturer:
TI
Quantity:
2 000
Part Number:
DP83848IVVX/NOPB
Manufacturer:
TI
Quantity:
1 000
Part Number:
DP83848IVVX/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
Part Number:
DP83848IVVX/NOPB
0
Company:
Part Number:
DP83848IVVX/NOPB
Quantity:
15 000
3.4.3 Serial Management Preamble Suppression
The DP83848I supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis-
ter (BMSR, address 01h.) If the station management entity
(i.e. MAC or other management controller) determines that
all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management
entity need not generate preamble for each management
transaction.
The DP83848I requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
Read Operation
Write Operation
MII Management
MDIO
MDIO
MDC
MDC
MDIO
Serial Protocol
(STA)
(PHY)
(STA)
Z
Idle
Z
Idle
Z
Z
0
0
Start
Start
1 1
1
Opcode
(Read)
Opcode
(Write)
0
0 0
1
0
(PHYAD = 0Ch)
(PHYAD = 0Ch)
PHY Address
PHY Address
1 1 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Figure 5. Typical MDC/MDIO Write Operation
Figure 4. Typical MDC/MDIO Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Table 5. Typical MDIO Frame Format
Register Address
Register Address
(00h = BMCR)
(00h = BMCR)
Z
Z
Z
23
1
TA
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
TA
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre-
amble Suppression is supported.
While the DP83848I requires an initial preamble sequence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transac-
tion. A minimum of one idle bit between management
transactions is required as specified in the IEEE 802.3u
specification.
0 0 0
0 0
0 0 0
Register Data
Register Data
0
0 0 0 0 0 0 0 0
www.national.com
Z
Idle
Z
Z
Idle
Z

Related parts for DP83848IVV