4306-0 Peregrine Semiconductor, 4306-0 Datasheet - Page 7

• Manufacturer Part Number: 4306-0
• Description: KIT EVAL FOR 4306 RF DSA
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™r
• Type: Attenuatorr

Specifications of 4306-0

• Frequency: 0Hz ~ 4GHz
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: PE4306
• Other names: 4306-00

PE4306
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4306 DSA.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of
the internal negative voltage generator is desired,
then connect –VDD (black banana plug) to
ground. If an external –VDD is desired, then apply
-3V.
J1 should be connected to the LPT1 port of a PC
with the supplied control cable. The evaluation
software is written to operate the DSA in serial
mode, so switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the power up options, first disconnect
the control cable from the evaluation board. The
control cable must be removed to prevent the PC
port from biasing the control pins.
During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
attenuation is set to the value present on the five
control bits on the five parallel data inputs (C1 to
C16). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
Pin 20 is open and can be connected to any bias.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to pins 1 & 3
(Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
Document No. 70-0160-04 │ www.psemi.com
J4
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Figure 15. Evaluation Board Layout
Peregrine Specification 101/0112
Figure 16. Evaluation Board Schematic
Peregrine Specification 102/0144
Note: Resistors on pins 1 and 3 are required and should be placed as
1
DATA
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
C16
close to the part as possible to avoid package resonance and
meet error specifications over frequency.
Z=50 Ohm
CLK
LE
10kohm
10 kohm
VCC
1
2
3
4
5
C16
RFin
DATA
CLK
LE
C1
QFN4X4
100 pF
U1
C2
RFout
VNEG
GND
C4
C8
PS
15
14
13
12
11
C8
PS
Z=50 Ohm
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