OM13014,598 NXP Semiconductors, OM13014,598 Datasheet
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LPC11U1x 32-bit ARM Cortex-M0 microcontroller flash SRAM; USB device; USART Rev. 1 — 11 April 2011 1. General description The LPC11U1x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller ...
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... NXP Semiconductors Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. High-current source output driver (20 mA) on one pin (P0_7). High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5). ...
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... NXP Semiconductors 3. Applications Consumer peripherals Medical Industrial control 4. Ordering information Table 1. Ordering information Type number Package Name LPC11U12FHN33/201 HVQFN33 LPC11U12FBD48/201 LQFP48 LPC11U13FBD48/201 LQFP48 LPC11U14FHN33/201 HVQFN33 LPC11U14FBD48/201 LQFP48 LPC11U14FET48/201 TFBGA48 4.1 Ordering options Table 2. Ordering options Type number Flash ...
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... NXP Semiconductors 5. Block diagram LPC11U12/13/14 system bus HIGH-SPEED GPIO ports 0/1 GPIO RXD TXD (1) (1) (1) DCD , DSR , RI SMARTCARD INTERFACE CTS, RTS, DTR SCLK CT16B0_MAT[1:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 (2) CT32B1_CAP[1:0] WINDOWED WATCHDOG ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO1_19/DTR/SSEL1 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration (HVQFN33) LPC11U1X Objective data sheet terminal 1 index area 1 RESET/PIO0_0 2 3 XTALIN 4 LPC11U1x XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 ...
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... NXP Semiconductors PIO1_25/CT32B0_MAT1 PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE XTALIN XTALOUT PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO1_26/CT32B0_MAT2/RXD PIO1_27/CT32B0_MAT3/TXD Fig 3. Pin configuration (LQFP48) LPC11U1X Objective data sheet LPC11U1x All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 LPC11U1x 32-bit ARM Cortex-M0 microcontroller 36 PIO1_13/DTR/CT16B0_MAT0/TXD 35 TRST/PIO0_14/AD3/CT32B1_MAT1 34 TDO/PIO0_13/AD2/CT32B1_MAT0 ...
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... NXP Semiconductors Fig 4. Pin configuration (TFBGA48) LPC11U1X Objective data sheet ball A1 LPC11U1x index area Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 LPC11U1x 32-bit ARM Cortex-M0 microcontroller 002aag101 © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 6.2 Pin description Table 3 shows all pins and their assigned digital or analog functions ordered by GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and PIO0_5 ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO0_4/SCL 10 PIO0_5/SDA 11 PIO0_6/USB_CONNECT/ 15 SCK0 PIO0_7/CTS 16 PIO0_8/MISO0/ 17 CT16B0_MAT0 PIO0_9/MOSI0/ 18 CT16B0_MAT1 SWCLK/PIO0_10/SCK0/ 19 CT16B0_MAT2 TDI/PIO0_11/AD0/ 21 CT32B0_MAT3 LPC11U1X Objective data sheet Reset Type state [1] [ I/O - I/O [ I/O - I I I I All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 3. Pin description Symbol TMS/PIO0_12/AD1/ 22 CT32B1_CAP0 TDO/PIO0_13/AD2/ 23 CT32B1_MAT0 TRST/PIO0_14/AD3/ 24 CT32B1_MAT1 SWDIO/PIO0_15/AD4/ 25 CT32B1_MAT2 PIO0_16/AD5/ 26 CT32B1_MAT3/WAKEUP PIO0_17/RTS/ 30 CT32B0_CAP0/SCLK LPC11U1X Objective data sheet Reset Type state [ I I/O All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO0_18/RXD/ 31 CT32B0_MAT0 PIO0_19/TXD/ 32 CT32B0_MAT1 PIO0_20/CT16B1_CAP0 7 PIO0_21/CT16B1_MAT0/ 12 MOSI1 PIO0_22/AD6/ 20 CT16B1_MAT1/MISO1 PIO0_23/AD7 27 PIO1_0/CT32B1_MAT0 - PIO1_1/CT32B1_MAT1 - PIO1_2/CT32B1_MAT2 - LPC11U1X Objective data sheet Reset Type state [ I I All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO1_3/CT32B1_MAT3 - PIO1_4/CT32B1_CAP0 - PIO1_5/CT32B1_CAP1 - PIO1_6 - PIO1_7 - PIO1_8 - PIO1_9 - PIO1_10 - PIO1_11 - PIO1_12 - PIO1_13/DTR/ - CT16B0_MAT0/TXD PIO1_14/DSR/ - CT16B0_MAT1/RXD LPC11U1X Objective data sheet Reset Type state [ I/O [ I/O [ I/O [ I/O [ I/O [ I/O [ I All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO1_15/DCD/ 28 CT16B0_MAT2/SCK1 PIO1_16/RI/ - CT16B0_CAP0 PIO1_17/CT16B0_CAP1/ - RXD PIO1_18/CT16B1_CAP1/ - TXD PIO1_19/DTR/SSEL1 1 PIO1_20/DSR/SCK1 - PIO1_21/DCD/MISO1 - PIO1_22/RI/MOSI1 - LPC11U1X Objective data sheet Reset Type state [ I I I I I/O All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 3. Pin description Symbol PIO1_23/CT16B1_MAT1/ - SSEL1 PIO1_24/CT32B0_MAT0 - PIO1_25/CT32B0_MAT1 - PIO1_26/CT32B0_MAT2/ - RXD PIO1_27/CT32B0_MAT3/ - TXD PIO1_28/CT32B0_CAP0/ - SCLK PIO1_29/SCK0/ - CT32B0_CAP1 PIO1_31 - USB_DM 13 USB_DP 14 XTALIN 4 LPC11U1X Objective data sheet Reset Type state [ I I/O [ I I [8][ All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 3. Pin description Symbol XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. [2] See Figure 31 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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... NXP Semiconductors Table 4. Peripheral SSP0 SSP1 CT16B0 CT16B1 CT32B0 CT32B1 ADC USB CLKOUT LPC11U1X Objective data sheet Multiplexing of peripheral functions Function Type Default Available on ports SCK0 I/O no SSEL0 I/O no MISO0 I/O no MOSI0 I/O no SCK1 I/O no SSEL1 I/O no MISO1 I/O no MOSI1 I/O ...
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... NXP Semiconductors Table 4. Peripheral JTAG SWD 7. Functional description 7.1 Memory map The LPC11U1x incorporates several distinct memory regions, shown in the following figures. Figure 5 program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area size and is divided to allow for up to 128 peripherals. ...
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... NXP Semiconductors LPC11U12/13/ reserved private peripheral bus reserved GPIO reserved USB APB peripherals 1 GB reserved 2 kB USB RAM reserved 0.5 GB reserved 16 kB boot ROM reserved 4 kB SRAM reserved 32 kB on-chip flash (LPC11U14 on-chip flash (LPC11U13 on-chip flash (LPC11U12 Fig 5. LPC11U1x memory map 7 ...
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... NXP Semiconductors • Software interrupt generation. 7.2.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.3 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function ...
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... NXP Semiconductors 7.5.1 Full-speed USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer ...
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... NXP Semiconductors 7.7 SSP serial I/O controller The SSP controllers are capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master ...
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... NXP Semiconductors 7.9 10-bit ADC The LPC11U1x contains one ADC single 10-bit successive approximation ADC with eight channels. 7.9.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range 10-bit conversion time 2.44 s. ...
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... NXP Semiconductors 7.11 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.12 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window ...
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... NXP Semiconductors IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL clock select) system oscillator USB PLL USBPLLCLKSEL (USB clock select) Fig 6. LPC11U1x clocking generation block diagram 7.13.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU ...
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... NXP Semiconductors 7.13.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U1x, the system oscillator must be used to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency the maximum CPU operating frequency, by the system PLL ...
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... NXP Semiconductors on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.13.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile ...
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... NXP Semiconductors 7.13.5.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC11U1x can wake up from Deep power-down mode via the WAKEUP pin. The LPC11U1x can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block ...
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... NXP Semiconductors 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Conditions V supply voltage (core DD and external rail) I supply current Active mode executed from flash; Sleep mode; V system clock = 12 MHz Deep-sleep mode Power-down mode Deep power-down mode; ...
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... NXP Semiconductors Table 6. Static characteristics …continued +85 C, unless otherwise specified. amb Symbol Parameter Conditions I LOW-level output V OL current I HIGH-level short-circuit V OHS output current I LOW-level short-circuit V OLS output current I pull-down current pull-up current High-drive output pin (PIO0_7) I LOW-level input current V ...
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... NXP Semiconductors Table 6. Static characteristics …continued +85 C, unless otherwise specified. amb Symbol Parameter Conditions 2 I C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output V OL current as standard mode pins I LOW-level output ...
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... NXP Semiconductors [7] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [8] IRC disabled; system oscillator enabled; system PLL enabled. [9] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. [10] Including voltage on outputs in 3-state mode. ...
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... NXP Semiconductors Table 7. ADC static characteristics +85 C unless otherwise specified; ADC frequency 4.5 MHz, V amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC11U1X Objective data sheet ...
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... NXP Semiconductors 9.1 BOD static characteristics Table 8. amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11U1x user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11U1x user manual): • ...
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... NXP Semiconductors X (X) Conditions: T internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally. Fig 8. Typical supply current versus regulator supply voltage V ...
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... NXP Semiconductors X (X) Conditions: V oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally. Fig 10. Typical supply current versus temperature in Sleep mode X (X) Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register ...
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... NXP Semiconductors X (X) Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = <tbd>; USB_DP and USB_DM pulled LOW externally. Fig 12. Typical supply current versus temperature in Power-down mode X (X) Fig 13. Typical supply current versus temperature in Deep power-down mode ...
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... NXP Semiconductors Table 9. Power consumption for individual analog and digital blocks The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed ...
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... NXP Semiconductors 9.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 Conditions: V Fig 14. High-drive output: Typical HIGH-level output voltage V output current (mA Conditions: V Fig 15. I LOW-level output voltage V LPC11U1X Objective data sheet °C 25 °C −40 ° 3 pin PIO0_7 0 pins PIO0_4 and PIO0_5. ...
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... NXP Semiconductors (mA) 10 Conditions: V Fig 16. Typical LOW-level output current I 3 (V) 3.2 2.8 2.4 Conditions: V Fig 17. Typical HIGH-level output voltage V I LPC11U1X Objective data sheet 0.2 = 3.3 V; standard port pins and PIO0_7 °C 25 °C −40 ° 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors (μA) −10 −30 −50 −70 Conditions: V Fig 18. Typical pull-up current (μ Conditions: V Fig 19. Typical pull-down current I LPC11U1X Objective data sheet °C 25 °C −40 ° 3.3 V; standard port pins. DD versus input voltage °C 25 °C −40 ° 3.3 V; standard port pins. ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 10. amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 11. ...
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... NXP Semiconductors 10.3 Internal oscillators Table 12. amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. X (X) Conditions: Frequency values are typical values. 12 MHz <tbd> % accuracy is guaranteed for 2.7 V ...
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... NXP Semiconductors 10.4 I/O pins Table 14. amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 15. Dynamic characteristic: I [ +85 C. amb Symbol Parameter f SCL clock SCL frequency t fall time f t LOW period of the LOW SCL clock ...
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... NXP Semiconductors could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t [8] The maximum t HD;DAT transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. ...
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... NXP Semiconductors 10.6 SSP interface Table 16. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter SSP master T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time h(Q) SSP slave T PCLK cycle time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP master timing in SPI mode LPC11U1X Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI DATA VALID MISO t v(Q) DATA VALID DATA VALID MOSI t DS DATA VALID DATA VALID MISO All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP slave timing in SPI mode LPC11U1X Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t DS MOSI DATA VALID DATA VALID t v(Q) MISO DATA VALID DATA VALID All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10.7 USB interface Table 17. Dynamic characteristics: USB pins (full-speed) pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC11U1x Fig 26. USB interface on a self-powered device LPC11U1x Fig 27. USB interface on a bus-powered device 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... NXP Semiconductors Fig 28. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 28), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. ...
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... NXP Semiconductors Table 18. Fundamental oscillation frequency F 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 19. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane ...
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... NXP Semiconductors 11.4 Standard I/O pad configuration Figure 30 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output driver pin configured as digital input pin configured as analog input Fig 30 ...
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... NXP Semiconductors 11.5 Reset pad configuration reset Fig 31. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11U1x chip. ...
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... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 7.1 mm nom 0.85 0.02 0.28 0.2 7.0 min 0.80 0.00 0.23 6 ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.6 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm ball A1 index area ball index area Dimensions Unit max 1.10 0.30 0.80 0.35 4.6 mm nom 0.95 0.25 0.70 0.30 4.5 min 0.85 0.20 0.65 0.25 4.4 ...
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... NXP Semiconductors 13. Abbreviations Table 20. Acronym A/D ADC AHB APB BOD GPIO JTAG PLL RC SPI SSI SSP TAP USART LPC11U1X Objective data sheet Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Joint Action Test Group ...
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... NXP Semiconductors 14. Revision history Table 21. Revision history Document ID Release date LPC11U1X v.1 20110411 LPC11U1X Objective data sheet Data sheet status Change notice Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 April 2011 LPC11U1x 32-bit ARM Cortex-M0 microcontroller ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC11U1X Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 17 7.1 Memory map 7.2 Nested Vectored Interrupt Controller (NVIC 7.2.1 Features ...