WD1SN256X808-400C-PN Wintec Industries, WD1SN256X808-400C-PN Datasheet - Page 7

• Manufacturer Part Number: WD1SN256X808-400C-PN
• Description: MODULE DDR-400 256MB 200-SODIMM
• Manufacturer: Wintec Industries
• Series: -r

Specifications of WD1SN256X808-400C-PN

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MHz
• Features: -
• Package / Case: 200-SODIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Address and control input
hold time
Address and control input
setup time
Read preamble
Read postamble
Active bank A to Active
bank B command
Write recovery time
Auto Precharge write
recovery + Precharge time
Internal Write to Read
command delay
Exit Self-Refresh to non-
Read command
Exit Self-Refresh to Read
command
Average periodic refresh
interval
V
Note:
Green Rev. 1.1 - March, 06
DD
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
11. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
= +2.5V ± 0.2V, V
Parameter
Input slew rate ≥ 1 V/ns for DDR400 and DDR333
The CK/
level for signals other than CK/
Inputs are not recognized as valid until V
The output timing reference level, as measured at the timing reference point indicated in AC Characteristics is V
For each of the terms, if not already an interger, round to the next highest interger. tCK is equal to the actual system clock cycle time.
These parameters guarantee device timing, but they are not necessarily tested on each device.
tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK and
measured between V
A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
performance (bus turnaround) degrades accordingly.
CK
input reference level (for timing reference to CK/
DD
IH(ac)
Q = +2.5V ± 0.2V, V
tIH
tIS
tRPRE
tRPST
tRRD
tWR
tDAL
tWTR
tXSNR
tXSRD
tREFI
Symbol
and V
CK
IL(ac)
.
, is V
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.
Min.
200
0.6
0.7
0.6
0.7
0.9
0.4
10
75
15
DDR-400
2
-
REF
REF
. CK/
-5
stabilizes.
Max.
SS
1.1
0.6
7.8
-
-
-
-
-
-
-
-
-
CK
= 0V
One Rank, x8 Non-ECC SODIMM Pb-free
slew rate are ≥ 1 V/ns.
Min.
0.75
0.75
200
0.8
0.8
0.9
0.4
12
15
75
DDR-333
(tWR/tCK )+ (tRP/tCK)
1
-
7
-6
CK
Max.
1.1
0.6
7.8
) is the point at which CK and
-
-
-
-
-
-
-
-
-
DDR-266, 333, 400MHz, 64-bit
Min.
200
0.9
1.0
0.9
1.0
0.9
0.4
DDR-266
15
15
75
1
-
-7
Max. Min.
1.1
0.6
7.8
-
-
-
-
-
-
-
-
-
200
DDR-266B
0.9
1.0
0.9
1.0
0.9
0.4
15
15
75
1
-
-7.5
CK
CK
Max.
 2006 Wintec Industries, Inc.
1.1
0.6
7.8
cross: the input reference
slew rate > 1.0 V/ns,
-
-
-
-
-
-
-
-
-
TT
Unit
tCK
tCK
tCK
tCK
tCK
.
ns
ns
ns
ns
ns
ns
ns
µs
rate 2,3,4,5,8
rate 2,3,4,5,8
rate 2,3,4,5,8
rate 2,3,4,5,8
Slow slew
Slow slew
Fast slew
Fast slew
1,2,3,4,5
1,2,3,4,9
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
Note