DS33X42+ Maxim Integrated Products, DS33X42+ Datasheet - Page 367

• Manufacturer Part Number: DS33X42+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X42+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at
JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the controller
to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the
instruction parallel output. Instructions supported by the device and its respective operational binary codes are
shown in
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture
13.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into the
boundary scan register via JTDI using the Shift-DR state.
13.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
13.2.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR will sample all
digital inputs into the boundary scan register.
13.2.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
13.2.5 HIGHZ
All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between
JTDI and JTDO.
13.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code is loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
SAMPLE:PRELOAD
INSTRUCTION
Table
BYPASS
EXTEST
IDCODE
CLAMP
HIGHZ
13-1.
SELECTED REGISTER
Device Identification
Boundary Scan
Boundary Scan
Bypass
Bypass
Bypass
INSTRUCTION CODES
010
111
000
011
100
001
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