DS33W11+ Maxim Integrated Products, DS33W11+ Datasheet - Page 230

• Manufacturer Part Number: DS33W11+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33W11+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5 Packet Processor (Encapsulator) Registers
Note that some devices in the product family have less than four encapsulators. The DS33X11 contains only
Encapsulator #1. The DS33W41 and DS33X42 devices contain only encapsulators #1 and #3.
Register Name:
Register Description:
Register Address:
201h:
Default
200h:
Default
Bit 15: Encapsulator GFP CRC Mode(EGCM)
Bit 14: Encapsulator Protocol Selection (EPRTSEL)
Bit 13: Encapsulator Frame Check Sequence Append Disable (EFCSAD) When set to 1, frames will not have a
HDLC/GFP FCS appended prior to transmission. When equal to 0, the encapsulation FCS will be appended.
Bit 12: Encapsulator Scrambler Disable (ECFCRD) When set to 1, encapsulation X
Bit 11: Encapsulator 16-bit FCS Enable (EFCS16EN) – When set to 1, the HDLC Encapsulation uses a 16-bit
FCS. When equal to 0, a 32 bit FCS is appended. This bit only applies when EFCSAD = 0.
Bit 9: Encapsulator Ethernet FCS Bypass (EFCSB) When set to 1, the Ethernet FCS is forwarded exactly as
received. When equal to 0, the Ethernet FCS is removed prior to encapsulation.
Bit 8: Encapsulator Bit Byte Synchronous (EBBYS) When set to 1, the Encapsulator performs Byte Stuffing.
When equal to 0, the Encapsulator performs Bit Stuffing. When in GFP mode (EPRTSEL = 0), this bit should be set
to 1. Bit-stuffed HDLC is not valid for multi-member VCGs.
Bit 7: Encapsulator Interframe Idle Selection (EIIS) When set to 1, the Encapsulator Idle sequence is 0xFF.
When equal to 0, the Encapsulator Idle sequence is 0x7E. This bit only applies when EPRTSEL = 1.
Bit 6: Encapsulator Line Header Enable (ELHDE) When set to 1, the Encapsulator will insert the values in
PP.ELHHR and PP.ELHLR as a 4-byte Line Header. The header is appended after the PLI+CHEC field in GFP
mode, and after the start flag in HDLC mode.
Bit 5: Encapsulator Tag 1 Enable (ET1E) When set to 1, the Encapsulator will insert the values in PP.ET1DHR
and PP.ET1DLR as a 4-byte tag immediately before the DA field.
Bit 4: Encapsulator Tag 2 Enable (ET2E) When set to 1, the Encapsulator will insert the values in PP.ET2DHR
and PP.ET2DLR as a 4-byte tag immediately after the SA field.
Bits 2-3: Encapsulator Remove Enable (ERE[1:0])
Bit 1: Transmit Bit Reorder (TBRE) Controls the endian order of HDLC transmission. This bit function is not
available in device revision A1 (GL.IDR.REVn=000).
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
0= GFP Null. Encapsulator pFCS calculation begins with the 9
1= GFP Linear. Encapsulator pFCS calculation begins with the 13
0= GFP
1= HDLC/cHDLC/LAPS(X.86)
00 = Normal operation.
01 = 18 bytes are removed from the frame prior to encapsulation, starting with the DA field.
10 = 14 bytes are removed from the frame prior to encapsulation, starting with the DA field.
11 = Reserved.
EGCM
Bit 15
Bit 7
EIIS
0
0
EPRTSEL
ELHDE
Bit 14
Bit 6
0
0
PP.EMCR
Encapsulator Master Control Register
200h (+ 040h x (n-1), WAN Group Encapsulator n=1 to 4)
EFCSAD
Bit 13
ET1E
Bit 5
0
0
ECFCRD
Bit 12
ET2E
Bit 4
0
0
EFCS16EN
ERE1
Bit 11
Bit 3
0
0
th
byte after the start of the frame.
th
byte after the start of the frame.
Bit 10
ERE0
Bit 2
0
0
-
43
+1 scrambling is disabled.
EFCSB
TBRE
Bit 9
Bit 1
0
0
EHCBO
EBBYS
230 of 375
Bit 8
Bit 0
0
0