BD8966FVM-TR Rohm Semiconductor, BD8966FVM-TR Datasheet - Page 11

• Manufacturer Part Number: BD8966FVM-TR
• Description: IC SWITCHING REG W/MOSFET MSOP8
• Manufacturer: Rohm Semiconductor
• Series: -r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of BD8966FVM-TR

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 1 V ~ 2.5 V
• Current - Output: 800mA
• Frequency - Switching: 1MHz
• Voltage - Input: 4 V ~ 5.5 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2010 ROHM Co., Ltd. All rights reserved.
BD8966FVM
www.rohm.com
Phase
Phase
V
4. Determination of RITH, CITH that works as a phase compensator
[deg]
[deg]
5. Determination of output voltage
Gain
Gain
[dB]
[dB]
CC
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
The output voltage V
V
With R1 and R2 adjusted, the output voltage may be determined as required.
(Adjustable output voltage range: 1.0V～2.5V)
Use 1 kΩ～100 kΩ resistor for R1. If a resistor of the resistance higher than
100 kΩ is used, check the assembled set carefully for ripple voltage etc.
OUT
-90
-90
A
0
0
A
0
0
=(R2/R1+1)×V
fz
(Amp.)
V
Fig.29 Error amp phase compensation characteristics
R
C
OUT
Cin
ITH
ITH
= fp
2π×R
I
OUT
Fig.30 Typical application
fp(Min.)
(Min.)
fz(Amp.)
Fig.28 Open loop gain characteristics
Min.
EN
V
ITH
ITH
ADJ
OUT
OUT
1
fp(Max.)
×C
・・・(7) V
is determined by the equation (7):
I
ITH
OUT
V
GND,PGND
CC
Max.
,PV
CC
=
fz(ESR)
ADJ
SW
2π×R
: Voltage at ADJ terminal (0.8V Typ.)
OMax.
L
ESR
C
1
O
×C
O
11/14
fp=
fz
Pole at power amplifier
Zero at power amplifier
(ESR)
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
R
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
O
2π×R
=
V
OUT
2π×E
1
O
fp
fp
fz
×C
1
(Amp.)
(Min.)
(Max.)
SR
O
×C
=
=
=
O
2π×R
2π×R
2π×R
Fig.31 Determination of output voltage
1
6
SW
ADJ
OMax.
OMin.
ITH
1
1
1
×C
×C
×C
ITH
O
4.7µH
O
[Hz]←with lighter load
[Hz] ←with heavier load
10µF
Technical Note
2010.04 - Rev.B
R2
R1
Output