PI7C8152BMAIE Pericom Semiconductor, PI7C8152BMAIE Datasheet - Page 7
PI7C8152BMAIE
Manufacturer Part Number
PI7C8152BMAIE
Description
IC PCI-PCI BRIDGE 2PORT 160-MQFP
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8152AMAE.pdf
(90 pages)
Specifications of PI7C8152BMAIE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
160-MQFP, 160-PQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
13
14
13.1
13.2
14.1
14.2
14.3
12.1.5
12.1.6
12.1.7
12.1.8
12.1.9
12.1.10
12.1.11
12.1.12
12.1.13
12.1.14
12.1.15
12.1.16
12.1.17
12.1.18
12.1.19
12.1.20
12.1.21
OFFSET 28h ....................................................................................................................................... 74
12.1.22
OFFSET 2Ch....................................................................................................................................... 74
12.1.23
12.1.24
12.1.25
12.1.26
12.1.27
12.1.28
12.1.29
12.1.30
12.1.31
4Ch
12.1.32
12.1.33
12.1.34
12.1.35
12.1.36
12.1.37
12.1.38
12.1.39
12.1.40
12.1.41
12.1.42
13.2.1
13.2.2
13.2.3
13.2.4
BRIDGE BEHAVIOR.................................................................................................................... 85
ELECTRICAL AND TIMING SPECIFICATIONS................................................................... 87
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES................................................................ 85
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 86
MAXIMUM RATINGS ............................................................................................................... 87
DC SPECIFICATIONS ................................................................................................................ 87
AC SPECIFICATIONS ................................................................................................................ 87
REVISION ID REGISTER – OFFSET 08h ...................................................................... 70
CLASS CODE REGISTER – OFFSET 08h....................................................................... 70
CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 70
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 70
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 70
MASTER ABORT................................................................................................................ 86
PARITY AND ERROR REPORTING ................................................................................ 86
REPORTING PARITY ERRORS ....................................................................................... 86
SECONDARY IDSEL MAPPING ...................................................................................... 86
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 71
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 71
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 71
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 71
I/O BASE ADDRESS REGISTER – OFFSET 1Ch ...................................................... 71
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ..................................................... 72
SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 72
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ........................................... 73
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h.......................................... 73
PEFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ............. 73
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ......... 73
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 74
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 74
ECP POINTER REGISTER – OFFSET 34h................................................................. 74
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 75
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 75
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 76
ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 78
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 78
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 79
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 80
P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 81
PORT OPTION REGISTER – OFFSET 74h ................................................................ 81
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 83
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 84
CAPABILITY ID REGISTER – OFFSET DCh............................................................. 84
NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 84
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 84
POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 84
PPB SUPPORT EXTENSIONS REGISER – OFFSET E0h ........................................ 85
.......................................................................................................................................... 79
Page 7 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B