LTC4310CMS-2#TRPBF Linear Technology, LTC4310CMS-2#TRPBF Datasheet - Page 12

• Manufacturer Part Number: LTC4310CMS-2#TRPBF
• Description: IC I2C ISOLATR 400KHZ BUS 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap I²C Isolatorsr

Specifications of LTC4310CMS-2#TRPBF

• Tx/rx Type: I²C Logic
• Capacitance - Input: 10pF
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 7mA
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -

LTC4310-1/LTC4310-2
quiet if it has been idle high for at least 115µs, or if a STOP
bit has occurred and both data and clock have remained
high since the STOP bit. This functionality makes the
LTC4310 ideal for hot-swapping cards into and out of a
live I
and bus idle comparators are 0.5 • V
Stuck Bus Disconnect and Recovery
An internal timer runs whenever SDA, SCL or both are low.
The timer is only reset when both SDA and SCL are high. If
the timer does not reset within 37ms, the LTC4310 assumes
the bus is stuck low. Accordingly, it ceases driving its SDA
and SCL pins and transmits a special message across the
barrier to inform the other LTC4310. Upon receiving this
message, the other LTC4310 also ceases driving its SDA
and SCL pins. At least 40µs after determining the bus
is stuck low, the LTC4310 generates up to sixteen clock
cycles on SCL in an attempt to make the slave release
the SDA line. The LTC4310 stops issuing clocks when the
SDA line releases high, or after sixteen cycles, whichever
comes first. Once the clock pulses have completed, the
LTC4310 issues a STOP bit on SDA and SCL to reset all
devices on the bus.
The LTC4310 reactivates its amplifiers and rise time ac-
celerators when the bus releases high and a STOP bit or
bus idle occurs on both the local and isolated buses, as
previously described in the Start-Up, Data and Clock Hot
Swap Circuitry section. The stuck bus disconnect and re-
covery circuitry is disabled when the LTC4310 is in UVLO,
thermal shutdown and low current shutdown.
Transmit and Receive Circuitry
Transmissions occur on the TXP and TXN pins whenever
the externally driven SDA or SCL logic state changes – in
other words, transmissions are event driven. In addition,
if SDA and SCL do not change state for 1.15ms, the
LTC4310 retransmits the logic state. The TXP and TXN pins
are driven in a pseudo differential fashion. Both pins are
driven to ground when inactive and are driven to 1.25V
(typical) in matched sets of alternating 35ns pulses to send
information across the barrier to the other LTC4310.
The LTC4310 receives and decodes the pulses sent by the
other LTC4310 on its RXP and RXN pins. Assuming the
start-up sequence previously described has been com-
applicaTions inForMaTion

2
C system. The threshold voltages for the STOP bit
CC
.
If the LTC4310 has not received a message in 4.6ms, it
assumes there is a communication problem and ceases
driving its SDA and SCL pins. It also transmits a special
message to the other LTC4310 to inform it that it is no
longer driving its SDA and SCL bus. Upon receiving this
message, the other LTC4310 also ceases driving its SDA and
SCL pins. Once the communication problem is resolved,
both LTC4310’s reactivate their amplifiers and rise time
accelerators after a STOP bit or bus idle has occurred on
both buses, as previously described in the Start-Up, Data
and Clock Hot Swap Circuitry section.
Thermal Shutdown
If the die temperature of the LTC4310 exceeds 150°C, the
LTC4310 enters a thermal shutdown mode. It sets TXP
and TXN to a high impedance state, ceases driving SDA
and SCL, and ignores the signals on RXP and RXN. When
the temperature drops back below 130°C, the LTC4310
goes through the POR sequence previously described.
pleted, the LTC4310 drives its SDA and SCL lines to the
logic state dictated by the decoded RXP and RXN signals.
The LTC4310 rejects RXP and RXN signals having less
than 500mV magnitude to provide noise immunity against
common-mode transients.The parasitic capacitances of the
LTC4310’s RXP and RXN pins and their associated board
traces form a capacitive divider with the transmit/receive
coupling capacitors, as shown in Figure 6. To guarantee
robust communications, minimize the parasitic capacitance
CPAR by minimizing the trace length from the coupling
capacitors to the RXP and RXN pins and choose coupling
capacitor values, CRXP and CRXN, that are at least ten
times larger than CPAR.
Figure 6. Parasitic Trace and Pin Capacitances
Form a Capacitive Divider with C
Ensure C
≥47pF
≥47pF
CRXP
CRXN
RXP
, C
RXN
CPAR1
4.7pF
CPAR2
4.7pF
≥ 10 • C
PAR
RXP
RXN
LTC4310
GND
RXP
431012 F06
and C
RXN
.
431012f