MAX3680EAI+ Maxim Integrated Products, MAX3680EAI+ Datasheet - Page 4

• Manufacturer Part Number: MAX3680EAI+
• Description: IC DESERIALZR 622MBPS TTL 28SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3680EAI+

• Function: Deserializer
• Data Rate: 622Mbps
• Input Type: PECL
• Output Type: TTL
• Number Of Inputs: 1
• Number Of Outputs: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
4
16, 20, 23,
15, 17, 19,
21, 22, 24,
MAX3680
14, 18, 25
1, 2, 5, 8,
9, 11, 12,
_______________________________________________________________________________________
26, 28
27
10
13
—
3
4
6
7
PIN
MAX3680A
11, 12, 16,
15, 17, 19,
21, 22, 24,
14, 18, 25
20, 23, 27
1, 2, 5, 8,
26, 28
9, 10
13
—
3
4
6
7
Detailed Description
PD0–PD7
SCLK+
NAME
SCLK-
SYNC
PCLK
GND
SD+
N.C.
V
SD-
CC
+3.3V Supply Voltage
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Noninverting PECL Serial Clock Input
Inverting PECL Serial Clock Input
Ground
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
No Connection
TTL Parallel Clock Output
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
Figure 1. Functional Diagram
SCLK+
SCLK-
SYNC
SD+
SD-
FUNCTION
PECL
PECL
TTL
MAX3680A
MAX3680/
REGISTER
SHIFT
8-BIT
COUNTER
3-BIT
Pin Description
PARALLEL
REGISTER
OUTPUT
8-BIT
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK