DS90CR481VJD/NOPB National Semiconductor, DS90CR481VJD/NOPB Datasheet - Page 14

• Manufacturer Part Number: DS90CR481VJD/NOPB
• Description: IC SERIALIZER 48BIT 100-TQFP
• Manufacturer: National Semiconductor

Specifications of DS90CR481VJD/NOPB

• Function: Serializer/Deserializer
• Data Rate: 5.38Gbps
• Input Type: CMOS/TTL
• Output Type: LVDS
• Number Of Inputs: 48
• Number Of Outputs: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90CR481VJD; *DS90CR481VJD/NOPB; DS90CR481VJD

www.national.com
Applications Information
The DS90CR481/DS90CR482 chipset is improved over prior
generations of Channel Link devices and offers higher band-
width support and longer cable drive with three areas of
enhancement. To increase bandwidth, the maximum clock
rate is increased to 112 MHz and 8 serialized LVDS outputs
are provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. This
requires the use of one pull up resistor to Vcc; please refer to
Table 1 to set the level needed. Optional DC balancing on a
cycle-to-cycle basis, is also provided to reduce ISI (Inter-
Symbol Interference). With pre-emphasis and DC balancing,
a low distortion eye-pattern is provided at the receiver end of
the cable. A cable deskew capability has been added to
deskew long cables of pair-to-pair skew of up to
data bit time (up to 80 MHz clock rates). For details on
deskew, refer to “Deskew” section below. These three en-
hancements allow cables 5+ meters in length to be driven
depending upon media and clock rate.
The DS90CR481/482 chipset may also be used in a non-DC
Balance mode. In this mode pre-emphasis is supported. In
this mode, the chipset is also compatible with 21 and 28-bit
Channel Link Receivers. See Figure 16 for the LVDS map-
ping.
Note 9: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating
frequency.
2. DC Balance
In addition to data information an additional bit is transmitted
on every LVDS data signal line during each cycle as shown
in Figure 15. This bit is the DC balance bit (DCBAL). The
purpose of the DC Balance bit is to minimize the short- and
long-term DC bias on the signal lines. This is achieved by
selectively sending the data either unmodified or inverted.
The value of the DC balance bit is calculated from the
running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall
be calculated by subtracting the number of bits of value 0
from the number of bits value 1 in the current word. Initially,
the running word disparity may be any value between +7 and
−6. The running word disparity shall be calculated as a
continuous sum of all the modified data disparity values,
where the unmodified data disparity value is the calculated
1MΩ or NC
Frequency
112MHz
112MHz
80MHz
80MHz
66MHz
50kΩ
100Ω
Rpre
9kΩ
3kΩ
1kΩ
TABLE 1. Pre-emphasis DC voltage level with (Rpre)
TABLE 2. Pre-emphasis needed per cable length
±
Resulting PRE Voltage
1 LVDS
PRE Voltage
0.75V
1.0V
1.5V
2.0V
2.6V
1.0V
1.5V
1.0V
1.2V
1.5V
Vcc
14
NEW FEATURES DESCRIPTION
1. Pre-emphasis
Adds extra current during LVDS logic transition to reduce the
cable loading effects. Pre-emphasis strength is set via a DC
voltage level applied from min to max (0.75V to Vcc) at the
“PRE” pin. A higher input voltage on the ”PRE” pin increases
the magnitude of dynamic current during data transition. The
“PRE” pin requires one pull-up resistor (Rpre) to Vcc in order
to set the DC level. There is an internal resistor network,
which cause a voltage drop. Please refer to the tables below
to set the voltage level.
The waveshape at the Receiver input should not exhibit over
or undershoot with the proper amount of pre-emphasis set.
Too much pre-emphasis generates excess noise and in-
creases power dissipation. Cables less than 2 meters in
length typically do not require pre-emphasis.
data disparity minus 1 if the data is sent unmodified and 1
plus the inverse of the calculated data disparity if the data is
sent inverted. The value of the running word disparity shall
saturate at +7 and −6.
The value of the DC balance bit (DCBAL) shall be 0 when
the data is sent unmodified and 1 when the data is sent
inverted. To determine whether to send data unmodified or
inverted, the running word disparity and the current data
disparity are used. If the running word disparity is positive
and the current data disparity is positive, the data shall be
sent inverted. If the running word disparity is positive and the
current data disparity is zero or negative, the data shall be
sent unmodified. If the running word disparity is negative and
the current data disparity is positive, the data shall be sent
unmodified. If the running word disparity is negative and the
Typical cable length
100% pre-emphasis
50% pre-emphasis
Standard LVDS
5+ meters
2 meters
5 meters
2 meters
7 meters
Effect