AD9845BJST Analog Devices Inc, AD9845BJST Datasheet - Page 12

• Manufacturer Part Number: AD9845BJST
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9845BJST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Current - Supply: -

AD9845B
HD
VD
HD
VD
PxGA GAIN
PxGA GAIN
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
0 = GAIN0, 1 = GAIN1, 2 = GAIN2
SHP
SHP
HD
VD
HD
VD
0101...
LINE 0
0101...
LINE 0
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323... (ODD).
NOTES
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
3ns MIN
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
0101...
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
LINE 1
1212...
LINE 1
EVEN FIELD
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
5 PIXEL MIN
FRAME N
5 PIXEL MIN
0101...
LINE 2
LINE 2
0101...
LINE M–1
LINE M–1
3ns MIN
GAINX
LINE M
LINE M
–12–
3ns MIN
GAINX
GAIN0
2323...
LINE 0
0101...
3ns MIN
LINE 0
GAIN1
GAIN0
GAIN0
GAIN1
2323...
LINE 1
1212...
LINE 1
ODD FIELD
GAINX
FRAME N+1
GAIN0
2323...
LINE 2
0101...
LINE 2
GAIN2
GAINX
LINE M–1
LINE M–1
GAIN3
GAIN1
GAIN2
LINE M
LINE M
REV. B