AD9844AJST Analog Devices Inc, AD9844AJST Datasheet - Page 5

• Manufacturer Part Number: AD9844AJST
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9844AJST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9844A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
Parameter
SAMPLE CLOCKS
DATA OUTPUTS
SERIAL INTERFACE
NOTES
1
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK DVSS
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
(10 sec)
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
Output Delay
Output Hold Time
Pipeline Delay
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
1
With
Respect
To
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
AVSS
AVSS
Min Max
–0.3 +3.9
–0.3 +3.9
–0.3 +3.9
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
(C
Serial Timing in Figures 8–10.)
L
= 20 pF, f
150
300
SAMP
= 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Unit
V
V
V
V
V
V
V
V
°C
°C
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
SCLK
CONV
ADC
SHP
SHD
CDM
COB
S1
S2
ID
INH
OD
H
LS
LH
DS
DH
DV
Model
AD9844AJST –20°C to +85°C
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 92°C
Min
48
20
7
7
4
2
0
20
10
7.0
10
10
10
10
10
10
Temperature
Range
ORDERING GUIDE
Typ
50
25
12.5
12.5
10
20
12.5
25
3.0
14.5
7.6
9
WARNING!
Max
16
Package
Description
Thin Plastic
Quad Flatpack
(LQFP)
ESD SENSITIVE DEVICE
AD9844A
Package
Option
ST-48
Unit
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns