MPR083QR2 Freescale Semiconductor, MPR083QR2 Datasheet - Page 6

• Manufacturer Part Number: MPR083QR2
• Description: IC CTLR TOUCH SENSOR PROX 16-QFN
• Manufacturer: Freescale Semiconductor
• Type: Capacitiver

Specifications of MPR083QR2

• Number Of Inputs/keys: 8 Slider
• Data Interface: I²C, Serial
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Supply: 1.62mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN Exposed Pad
• Output Type: Voltage
• Interface: I²C
• Input Type: Logic
• Supply Voltage: 3.3 V
• Dimensions: 5 mm L x 5 mm W x 1 mm H
• For Use With: DEMOMPR083 - BOARD DEMO FOR MPR083 CTLRKITMPR083EVM - KIT EVAL 8POSITION ROTARY TOUCH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPR083
6
2.3.2
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S)
condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave,
it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another
transmission.
2.3.3
One data bit is transferred during each clock pulse
2.3.4
The acknowledge bit is a clocked 9
byte transferred effectively requires 9 bits. The master generates the 9
the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is
transmitting to the MPR083, the MPR083 generates the acknowledge bit because the MPR083 is the recipient. When the
MPR083 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.
BY TRANSMITTER
Start and Stop Conditions
Bit Transfer
Acknowledge
BY RECEIVER
SDA
SCL
SDA
SCL
SDA
SDA
SCL
CONDITION
START
CONDITION
S
START
S
DATA LINE STABLE
th
DATA VALID
bit
(Figure
Figure 6. Start and Stop Conditions
1
8) which the recipient uses to handshake receipt of each byte of data. Thus each
(Figure
Figure 8. Acknowledge
Figure 7. Bit Transfer
DATA ALLOWED
7). The data on SDA must remain stable while SCL is high.
CHANGE OF
2
th
clock pulse, and the recipient pulls down SDA during
ACKNOWLEDGEMENT
CLOCK PULSE FOR
8
CONDITION
Freescale Semiconductor
STOP
P
9
Sensors