AD7151BRMZ Analog Devices Inc, AD7151BRMZ Datasheet - Page 18

• Manufacturer Part Number: AD7151BRMZ
• Description: IC CAP CONV 1CH ULT LP 10MSOP
• Manufacturer: Analog Devices Inc
• Type: Capacitance-to-Digital Converterr

Specifications of AD7151BRMZ

• Input Type: Voltage
• Output Type: Digital
• Interface: 2-Wire Serial
• Current - Supply: 120µA
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 12bit
• Sampling Rate: 100SPS
• Input Channel Type: Single Ended
• Data Interface: 2-Wire, I2C, Serial
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 70µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7151
SETUP REGISTER
8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Register Bit Map
Bit
Mnemonic
Default
Table 11. Setup Register Bit Descriptions
Bit
7
6
5
4
3
2
1
0
Address Pointer 0x0B
Mnemonic
RngH
RngL
–
Hyst
ThrSettling
Description
Range bits set the CDC input range and determine the step for the AutoDAC function.
This bit should be 0 for the specified operation.
Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode;
hysteresis is always disabled in the fixed threshold mode.
Determines the settling time constant of the data average and thus the settling time of the adaptive
thresholds.
The response of the average to an input capacitance step change (that is, response to the change in the CDC
output data) is an exponential settling curve characterized by the following equation:
where:
Average(N) is the value of average N complete CDC conversion cycles after a step change on the input
Average(0) is the value before the step change
TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of
2, by programming the ThrSettling bits.
See Figure 39.
RngH
Bit 7
0
RngH
TimeConst
Average
0
0
1
1
INPUT CAPACITANCE
(CDC DATA) CHANGE
(
N
RngL
Bit 6
)
=
Figure 39. Data Average Response to Data Step Change
0
=
2
(
Average
ThrSettlin
RngL
0
1
0
1
g
+
) 1
(
) 0
Bit 5
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–
0
+
Change
Capacitive Input Range (pF)
1 (
DATA AVERAGE RESPONSE
Bit 4
Hyst
−
0
e
N
/ TimeConst
0.5
2
1
4
)
Bit 3
TIME
ThrSettling (4-Bit Value)
Bit 2
AutoDAC Step (CAPDAC LSB)
0x0B
Bit 1
4
1
2
8
Bit 0