SI3014-KS Silicon Laboratories Inc, SI3014-KS Datasheet
SI3014-KS
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SI3014-KS Summary of contents
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... Available in two 16-pin small outline packages (AC’97 interface on Si3024 and phone-line interface on Si3014), the chipset eliminates the need for an analog front end (AFE), an isolation transformer, relays, opto-isolators, and 4-wire hybrid. The Si3038 dramatically reduces the number of discrete components and cost required to achieve compliance with global regulatory requirements ...
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Si3038 2 Rev. 2.01 ...
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... Resetting Si3038 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC-Link Digital Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Codec Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC-Link Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Appendix A—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Appendix B—CISPR22 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pin Descriptions: Si3024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Pin Descriptions—Si3014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Rev. 2.01 Si3038 Page ...
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... Notes: 1. The Si3038 specifications are guaranteed when the typical application circuit (including component tolerances) of Figure 19 on page 16 and any Si3024 and Si3014 are used. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. ...
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... The ring signal is guaranteed not to be detected below the minimum and is guaranteed to be detected above the maximum. 2. C15, R14, Z2, and Z3 not installed. See "Ringer Impedance" on page 25. Si3014 Note: The remainder of the circuit is identical to the one shown in Figure 19 on page 16. Figure 1. Test Circuit for Loop Characteristics = 0 to 70° ...
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Si3038 Table 3. DC Characteristics 4. 4. Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage ...
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Table 5. AC Characteristics (V = 3 Charge Pump Parameter Transmit Frequency Response Receive Frequency Response 1 Transmit Full Scale Level 1,2 Receive Full Scale Level 3 Dynamic Range 3 Dynamic Range ...
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Si3038 Table 6. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3024 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional ...
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Table 9. AC Link Timing Characteristics—Clocks (V = 3 Charge Pump Parameter BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter BIT_CLK High Pulse Width* BIT_CLK low Pulse Width* SYNC Frequency SYNC Period SYNC ...
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Si3038 Table 10. AC Link Timing Characteristics—Data Setup and Hold (V = 3 Charge Pump Parameter Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK SYNC SDATA_OUT SDATA_IN ...
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Table 12. AC Link Timing Characteristics— Low Power Mode Timing (V = 3 Charge Pump Parameter End of Slot 2 to BIT_CLK, SDATA_IN Low Figure 7. AC-Link Low Power Mode Timing Diagram ...
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Si3038 Table 14. Digital FIR Filter Characteristics—Transmit and Receive (V = 3 Charge Pump, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation ...
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Input Frequency—Hz Figure 9. FIR Receive Filter Response Input Frequency—Hz Figure 10. FIR Receive Filter Passband Ripple For Figures 9–12, all filter plots apply to a sample rate kHz. The filters scale with the sample rate ...
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Si3038 Input Frequency—Hz Figure 13. IIR Receive Filter Response Input Frequency—Hz Figure 14. IIR Receive Filter Passband Ripple For Figures 13–16, all filter plots apply to a sample rate kHz. The filters scale with the sample ...
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Input Frequency—Hz Figure 17. IIR Receive Group Delay Input Frequency—Hz Figure 18. IIR Transmit Group Delay Rev. 2.01 Si3038 15 ...
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No Ground Plane In DAA Section 24.576 MHz C10 C3 Z4 C34 C35 Y1 D3 BAV99 R8 R7 R15 ID1 MCLK/XIN GPIO_A 2 15 XOUT GPIO_B 3 14 BITCLK BIT_CLK ID1 ...
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... W, ±1% 2.2 kΩ, 1/10 W, ±5% 150 Ω, 1/16 W, ±5% 10 Ω, 1/10 W, ±5% Not Installed 0 Ω, 1/10 W Si3024 Si3014 Rev. 2.01 Si3038 Supplier(s) Novacap, Venkel, Johanson, Murata, Panasonic Novacap, Venkel, Johanson, Murata, Panasonic Novacap, Johanson, Murata, Panasonic Central Semiconductor Diodes Inc ...
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Si3038 Table 17. FCC Component Values—Si3036 Chipset 1 Component 2 C1, µ Elec/Tant, ±20% C6,C10,C16 C9,C28,C29 C11 3 C12 C7,C8,C13,C14,C18, C19,C20,C22 3 0.1 µ Elec/Tant/X7R, ±20% C23 2,4 C24,C25,C31,C32 5 C30 6 ...
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Analog Output Figure 20 illustrates an optional application circuit to support the analog output capability of the Si3038 for call progress monitoring purposes. The AOUT level can be set to 0 dB, –6 dB, –12 dB, and mute for both ...
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Si3038 Functional Description The Si3038 is an integrated chipset that provides a low- cost, isolated, silicon-based MC’97-compliant interface to the telephone line. The Si3038 complies with the AC’97 2.1 specification and requires only a few low-cost discrete components to achieve ...
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Table 19. Country Specific Register Settings (Continued) Register Country OHS Greece Guam Hong Kong Hungary Iceland India Indonesia Ireland Israel Italy 1 Japan 1 Jordan 1 Kazakhstan Kuwait Latvia Lebanon Luxembourg Macao 1,3 Malaysia Malta Mexico Morocco Netherlands New Zealand ...
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... When the Si3038 is initially powered up, the RESET pin should be asserted. When the RESET pin is deasserted, the registers will have default values. This reset condition guarantees the line-side chip (Si3014) is powered down with no possibility of loading the line (i.e., off-hook). An example initialization procedure is outlined below: 1 ...
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... The ISOcap communications link is disabled by default. The PR bits in register 3Eh must be cleared, and the sample rate must be set in register 40h/42h. No communication between the Si3024 and Si3014 can occur until these conditions are set. Off-Hook The communication system generates an off-hook command by writing a logic 1 to bit 0 (line 1) or bit 10 (line 2) of slot 12 ...
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... A positive ringing signal is defined as a voltage greater than the ring threshold across RNG1-RNG2. RNG1 and RNG2 are pins 5 and 6 of the Si3014. Conversely, a negative ringing signal is defined as a voltage less than the negative ring threshold across RNG1-RNG2. ...
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The length of this count (in seconds) is 65536 divided by the sample rate. The GPIO1(GPIO11) bit will also be reset to zero by an off-hook event. When RFWE is 1, the GPIO1(GPIO11) bit will toggle active low when ...
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... ADC overload condition. The PK BTD bit is set when a line signal (billing tone) is large enough to excessively reduce the internal power supply of the line-side device (Si3014). When the BTD bit is set, the dc termination is released to maintain an off hook condition, and the line is presented with an 800 Ω dc impedance. ...
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Power Down Fram e SYNC BIT_CLK SDATA_OUT slot 12 W rite to TAG prev. frame 56th s lot 12 SDATA_IN TAG prev. fram e Figure 24. AC-Link Power-Down/Up Sequence Although the DAA will remain off-hook during a billing tone event, ...
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... This mode is typically used to detect caller ID data (see the “Caller ID” section). The on-hook line monitor can also be used to detect whether a phone line is physically connected to the Si3014 and associated circuitry line is present and the LINE1_CID/LINE2_CID bit is set, SDATA_IN will have a near zero value and the LCS[3:0] bits will read 1111b ...
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... The external device receives the signal on the transmit pins. This mode allows testing of the Si3038s converters and external devices between the Si3014 and RJ-11 jack. To enable this mode, set the L1B[2:0](L2B[2:0]) = 001. The final two testing modes, local analog loopback and ...
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Si3038 SDATA_IN) to the transmit pin, which is looped externally to the receive pin. To enable external analog loopback, set L1B2:0 (L2B2:0) = 110. Both analog loopback modes require power, which is typically supplied by the loop current from TIP ...
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Digital AC'97 Controller Figure 27. Si3038 Connection To AC’97 Controller (Primary Device Configuration) AC-Link Digital Serial Interface Protocol The Si3024 incorporates a 5-pin digital serial interface that links it to the AC’97 controller. AC-link is a bi- directional, fixed rate, ...
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Si3038 Tag Phase SYNC 12.228 MHz 81.4 nS BIT_CLK Valid SDATA_OUT slot(1) slot(2) Frame End of previous Time Slot "Valid" Audio Frame Bits ("1" = Time slot contains valid PCM data) Figure 29. AC-Link Audio Output Frame The AC-link protocol ...
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SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits (bit SDATA_IN Slot 1) to set active (low). SLOTREQ bits asserted during the current audio input frame signal ...
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... Bit 1 LINE1_FDT Bit 0 GPIO_INT Slot 12: Modem GPIO Control Slot 12 contains latency critical signals for the Si3014 and the GPIO of the Si3024. See Table 22. Slots 3, 4, 6–9, 11: Not Used The Si3038 always pads audio output frame slots 3, 4, 6–9, and 11 with 0s. ...
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... Slot 10: Modem Line 2 ADC Audio input frame for Line 2. Slot 12: Modem GPIO Status Slot 12 contains latency critical signals for the Si3014 and the GPIO of the Si3024. Slot 12 also reflects the status of the link between the Si3024 and Si3014. See Table 22. 20.8 µ S ...
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Si3038 Codec Register Access Whenever the AC’97 Digital Controller addresses the Si3024 as a primary codec or the codec responds to a read command, Slot 0 Tag bits should always be set to indicate actual valid data in Slot 1 ...
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Table 25. Secondary Codec Register Access Slot 0 Bit Definitions Bit 15 Frame Valid 14 Slot 1: Valid Command Address bit (Primary Codec only) 13 Slot 2: Valid Command Data bit (Primary Codec only) 12–3 Slot 3: 12 Valid bits ...
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Si3038 Control Registers Note: Any register not listed here is reserved and should not be written. Undefined/unimplemented registers return 0. Register Name D15 D14 D13 D12 D11 D10 3Ch Extended ID1 ID0 Modem ID 3Eh Extended PRF Modem Sta- tus ...
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Register 3Ch Extended Modem ID D15 D14 D13 D12 D11 ID1 ID0 Reset settings (dependent on pins ID1 and ID0) = 0001 Bit Name 15 ID1 ID1, ID0 is a 2-bit field which indicates the Codec configuration: Primary is 00; ...
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... PRD Reset settings = 0xFF00 Bits 7–0 are read only, 1 indicates modem AFE subsystem readiness. Bits 13–8 are read/write and control modem AFE subsystem power-down. Note: When bits 13–8 are all set to 1, the Si3014 is powered down. Bit Name 15:14 Reserved Read returns one. ...
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... When set to zero, the internal PLL is disabled. The PLL should be programmed before the line side (Si3014) is activated via clearing any PR bit in register 3Eh. Furthermore, sleep mode is not supported when the PLL is disabled ...
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Si3038 Register 46h Line 1 DAC/ADC Level D15 D14 D13 D12 D11 Mute DAC3 DAC2 DAC1 Reset setting for Line 1 device = 0x8080 Reset setting for Line 2 device = 0x0000 This read/write register controls the modem AFE DAC ...
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Register 48h Line 2 DAC/ADC Level D15 D14 D13 D12 D11 Mute DAC3 DAC2 DAC1 Reset setting for Line 1 device = 0x0000 Reset setting for Line 2 device = 0x8080 This read/write register controls the modem AFE DAC and ...
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Si3038 Register 4Eh GPIO Pin Polarity and Type D15 D14 D13 D12 D11 GP15 GP14 GP13 GP12 GP11 GP10 Reset settings = 0xFFFF The GPIO Pin Polarity/Type register is read/write for selecting the polarity and type for Slot 12 I/O. ...
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Register 54h GPIO Pin Status D15 D14 D13 D12 D11 GI15 GI14 GI13 GI12 GI11 Reset settings = 0xxxxx GPIO Status is a read/write register that reflects the state of all GPIO pins (inputs and outputs) on slot 12. The ...
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Si3038 Register 56h Miscellaneous Modem AFE Status and Control D15 D14 D13 D12 D11 MLNK Reset settings = 0x0000 This read/write register defines the loopback modes available for the modem line ADCs/DACs. The default value after cold register reset (0xx000) ...
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... CBID Chip B (line side) ID Line-side is domestic Line-side has international support. 7:4 REVB[3:0] Chip Revision. Four-bit value indicating the revision of the Si3014 (line side) silicon. 0010 = Si3014 Rev B. 0011 = Si3014 Rev C. 3:0 REVA[3:0] Chip Revision. Four-bit value indicating the revision of the Si3024 (system-side) silicon ...
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Si3038 Register 5Ch Line Side Configuration 1 D15 D14 D13 D12 D11 ARM1 ARM0 ATM1 ATM0 IIRE Reset settings = 0xF010 Bit Name 15:14 ARM[1:0] Analog (Call Progress) Receive Path Mute dB –6 dB. 10 ...
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Bit Name 5 ACT AC Termination Select Selects the real impedance Selects the complex impedance. 4:3 DCT[1:0] DC Termination Select Reserved Japan Mode. Low voltage mode. (Transmit level = –3 dBm). 10 ...
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... BTE = 1 in Register 5Ch.) 7 CLE Communications (ISOcap) Error Indicates a communication problem between the Si3024 and Si3014. When it goes high, it remains high until a logic 0 is written to it. 6 FDT Frame Detect Indicates ISOcap communication has not established frame lock. ...
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Register 62h Line Side Configuration 2 D15 D14 D13 D12 D11 D10 Reset setting = 0x0000 Bit Name 15:9 Reserved Read returns zero. 8 DIAL DTMF Dialing Mode. This bit should be set during DTMF dialing in CTR21 mode if ...
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Si3038 Register 64h Line Side Configuration 3 D15 D14 D13 D12 D11 Reset setting = 0x0000 Bit Name 15:8 Reserved Read returns zero. 7 Reserved Read returns zero or one. 6:3 Reserved Read returns zero. 2 OVL Overload Detected. This ...
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A A— UL1 950 Designs using the Si3038 pass all overcurrent and over- voltage tests for UL1950 3rd Edition compliance with a couple of considerations. Figure 34 shows the designs that can ...
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Si3038 A B—CISPR22 Various countries are expected to adopt the IEC CISPR22 standard over the next few years. For example, the European Union (EU) has adopted a standard entitled EN55022, which is ...
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Pin Descriptions: Si3024 Si3024 (SOIC) MCLK/XIN 1 XOUT 2 BIT_CLK SDA TA _IN 5 SDA TA _OUT RESET SOIC TSSOP Pin Name Pin # Pin # 1 13 MCLK/XIN 2 14 ...
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Si3038 Table 28. 3024 Pin Descriptions (Continued) SOIC TSSOP Pin Name Pin # Pin # ID1 15 11 GPIO_B 16 12 GPIO_A 56 Description Analog Supply Voltage. Provides the analog supply voltage for the ...
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... Pin Descriptions—Si3014 Pin # Pin Name 1 QE2 Transistor Emitter 2. Connects to the emitter of Q4. 2 DCT DC Termination. Provides dc termination to the telephone network. 3 IGND Isolated Ground. Connects to ground on the line-side interface. Also connects to capacitor C2. 4 C1B Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. ...
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Si3038 Table 29. 3014 Pin Descriptions (Continued) Pin # Pin Name 14 RX Receive Input. Serves as the receive side input from the telephone network. 15 FILT Filter. Provides filtering for the dc termination circuits. 16 FILT2 Filter 2. Provides ...
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... Si3012-KS Si3021-KT Si3024-KS Si3012-KS Si3024-KT Si3024-KS Si3014-KS Si3024-KT Si3021-KS Si3015-KS Si3021-BS Si3015-BS Si3025-KS Si3012-KS Si3025-KS Si3014-KS Rev. 2.01 Si3038 Line Temperature (TSSOP) Si3014-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3014-KT 0°C to 70°C 0°C to 70°C – ...
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... Si3038 SOIC Outline Figure 36 illustrates the package details for the Si3024 and Si3014. Table 31 lists the values for the dimensions shown in the illustration Seating Plane Figure 36. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 31. Package Diagram Dimensions θ L Detail γ Symbol ...
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... TSSOP Outline Figure 37 illustrates the package details for the Si3024 and Si3014. Table 32 lists the values for the dimensions shown in the illustration Figure 37. 16-pin Thin Small Shrink Outline Package (TSSOP) Table 32. Package Diagram Dimensions θ Symbol Millimeters Min Nom Max A — ...
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Si3038 Rev 1.0 to Rev 1.1 Change List Typical Application Circuit was updated. C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table 16 and Table 17. In Table 17, the tolerance was ...
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Rev. 2.01 Si3038 63 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...