CS82C55A-5 Intersil, CS82C55A-5 Datasheet - Page 27
![IC I/O EXPANDER 24B 44PLCC](/photos/6/90/69044/cs82c55az96_sml.jpg)
CS82C55A-5
Manufacturer Part Number
CS82C55A-5
Description
IC I/O EXPANDER 24B 44PLCC
Manufacturer
Intersil
Datasheet
1.CS82C55AZ96.pdf
(29 pages)
Specifications of CS82C55A-5
Interface
Programmable
Number Of I /o
24
Interrupt Output
No
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Chip Configuration
8 Bit
Bus Frequency
5MHz
No. Of I/o's
24
Supply Voltage Range
4.5V To 5.5V
Digital Ic Case Style
LCC
No. Of Pins
44
Leaded Process Compatible
No
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Frequency - Clock
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS82C55A-5
Manufacturer:
INTERSIL
Quantity:
6 100
Company:
Part Number:
CS82C55A-5
Manufacturer:
INTERSIL
Quantity:
6 100
Company:
Part Number:
CS82C55A-5
Manufacturer:
INTERSIL
Quantity:
5 510
Part Number:
CS82C55A-5
Manufacturer:
INT
Quantity:
20 000
Company:
Part Number:
CS82C55A-5Z
Manufacturer:
ABB
Quantity:
101
Company:
Part Number:
CS82C55A-5Z
Manufacturer:
Intersil
Quantity:
468
j
E1
x 45
Ceramic Leadless Chip Carrier Packages (CLCC)
B
h x 45
E2
o
-E-
e
-F-
1
A
o
L
0.010
S
L2
E H
S
0.007
D3
D
D1
B1
27
M
-H-
D2
B2
E F
e
S H S
A1
L3
E3
0.010
PLANE 2
PLANE 1
B3
L1
E
S
E F
S
82C55A
J44.A
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
NOTES:
SYMBOL
1. Metallized castellations shall be connected to plane 1 terminals
2. Unless otherwise specified, a minimum clearance of 0.015 inch
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
4. The required plane 1 terminals and optional plane 2 terminals (if
5. The corner shape (square, notch, radius, etc.) may vary at the
6. Chip carriers shall be constructed of a minimum of two ceramic
7. Dimension “A” controls the overall package thickness. The maxi-
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
ND
NE
A1
B1
B2
B3
D1
D2
D3
E1
E2
E3
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
used) shall be electrically connected.
manufacturer’s option, from that shown on the drawing.
layers.
e1
L1
L2
L3
mum “A” dimension is package height before being solder dipped.
A
B
D
E
N
e
h
L
j
MIL-STD-1835 CQCC1-N44 (C-5)
0.064
0.054
0.033
0.022
0.006
0.640
0.640
0.015
0.045
0.045
0.075
0.003
MIN
-
-
0.500 BSC
0.250 BSC
0.500 BSC
0.250 BSC
0.050 BSC
0.072 REF
0.040 REF
0.020 REF
INCHES
11
11
44
0.120
0.088
0.039
0.028
0.022
0.662
0.662
0.662
0.662
0.055
0.055
0.095
0.015
MAX
-
16.26
16.26
1.37
0.84
0.56
0.15
1.14
1.14
1.90
0.08
1.63
0.38
MIN
MILLIMETERS
-
-
12.70 BSC
12.70 BSC
1.83 REF
6.35 BSC
6.35 BSC
1.27 BSC
1.02 REF
0.51 REF
11
11
44
16.81
16.81
16.81
16.81
3.05
2.24
0.99
0.71
0.56
1.40
1.40
2.41
0.38
MAX
-
November 16, 2006
Rev. 0 5/18/94
NOTES
FN2969.10
6, 7
2, 4
4
2
2
2
5
5
3
3
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-