PCA9500D,118 NXP Semiconductors, PCA9500D,118 Datasheet - Page 10

• Manufacturer Part Number: PCA9500D,118
• Description: IC I/O EXPANDER I2C 8B 16SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9500D,118

• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: EEPROM, POR
• Logic Family: PCA9500
• Number Of Lines (input / Output): 8.0 / 8.0
• Operating Supply Voltage: 2.5 V to 3.6 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Current: 25 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935271533118; PCA9500D-T; PCA9500D-T

NXP Semiconductors
8. Characteristics of the I
PCA9500_4
Product data sheet
8.1.1 START and STOP conditions
8.1 Bit transfer
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 15. Bit transfer
Fig 16. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 04 — 15 April 2009
16).
8-bit I
data valid
data line
stable;
2
C-bus and SMBus I/O port with 2-kbit EEPROM
Figure
allowed
change
of data
15).
STOP condition
mba607
PCA9500
P
© NXP B.V. 2009. All rights reserved.
mba608
10 of 26