MAX7318ATG+ Maxim Integrated Products, MAX7318ATG+ Datasheet - Page 10

• Manufacturer Part Number: MAX7318ATG+
• Description: IC I/O EXPANDER I2C 16B 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX7318ATG+

• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
Data is clocked into a register on the falling edge of the
acknowledge clock pulse. After reading the first byte,
additional bytes may be read and reflect the content in
the other register in the pair. For example, if input port 1
is read, the next byte read is input port 2. An unlimited
number of data bytes can be read in one read trans-
mission, but the final byte received must not be
acknowledged by the bus master.
The open-drain interrupt output, INT, activates when
one of the port pins changes states and only when the
pin is configured as an input. The interrupt deactivates
when the input returns to its previous state or the input
register is read (Figure 9). A pin configured as an out-
put does not cause an interrupt. Each 8-bit port register
is read independently; therefore, an interrupt caused by
port 1 is not cleared by a read of port 2’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of the input port register.
Figure 10. Simplified Schematic of I/Os
10
______________________________________________________________________________________
CONFIGURATION
SHIFT REGISTER
SHIFT REGISTER
WRITE PULSE
DATA FROM
DATA FROM
WRITE POLARITY
SHIFT REGISTER
PULSE
WRITE
READ PULSE
DATA FROM
POWER-ON
PULSE
RESET
CONFIGURATION
REGISTER
D
SET
CLR
Q
Q
OUTPUT PORT
REGISTER
D
CLR
Interrupt (INT)
SET
Q
Q
POLARITY INVERSION
INPUT PORT
REGISTER
REGISTER
D
D
CLR
CLR
SET
SET
Q
Q
Q
Q
When an I/O is configured as an input, FETs Q1 and Q2
are off (Figure 10), creating a high-impedance input with
a nominal 100kΩ pullup to V+. All inputs are overvoltage
protected to 5.5V, independent of supply voltage. When
a port is configured as an output, either Q1 or Q2 is on,
depending on the state of the output port register. When
V+ powers up, an internal power-on reset sets all regis-
ters to their respective defaults (Table 1).
The input port registers (Table 2) are read-only ports.
They reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or
an output by the respective configuration register. A
read of the input port 1 register latches the current
value of I/O0–I/O7. A read of the input port 2 register
latches the current value of I/O8–I/O15. Writes to the
input port registers are ignored.
Q1
Q2
100kΩ
POLARITY
REGISTER
DATA
Input/Output Port
Input Port Registers
OUTPUT PORT
REGISTER DATA
V
I/O PIN
GND
INPUT PORT
REGISTER DATA
TO INT
DD