PCA9675DK,118 NXP Semiconductors, PCA9675DK,118 Datasheet - Page 22

• Manufacturer Part Number: PCA9675DK,118
• Description: IC I/O EXPANDER I2C 16B 24QSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9675DK,118

• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4203-2; 935283228118; PCA9675DK-T

NXP Semiconductors
13. Dynamic characteristics
Table 6.
V
[1]
[2]
[3]
[4]
[5]
[6]
PCA9675_1
Product data sheet
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing; C
t
t
t
Interrupt timing; C
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
v(D)
d(rst)
DD
= 2.3 V to 5.5 V; V
t
t
C
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
SCL clock frequency
bus free time between a
STOP and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid time acknowledge
time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by the
input filter
data output valid time
data input setup time
data input hold time
data input valid time
reset delay time
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
[1]
L
f
100 pF (see
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
L
[6]
SS
100 pF (see
[2]
= 0 V; T
Figure 16
amb
f
.
Figure 16
= 40 C to +85 C; unless otherwise specified.
Conditions
and
Figure
and
Rev. 01 — 1 February 2007
Figure
17)
[4][5]
Remote 16-bit I/O expander for Fm+ I
17)
Standard mode
Min
300
250
4.7
4.0
4.7
4.0
0.3
4.7
4.0
0
0
0
4
-
-
-
-
-
-
I
2
C-bus
1000
Max
3.45
100
300
50
4
4
4
-
-
-
-
-
-
-
-
-
-
-
Fast mode I
20 + 0.1C
20 + 0.1C
Min
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
0
4
-
-
-
-
b
b
[3]
[3]
2
C-bus Fast mode Plus
Max
400
300
300
0.9
50
IL
4
4
4
-
-
-
-
-
-
-
-
-
-
-
of the SCL signal) in order to
2
C-bus with interrupt
0.26
0.26
0.26
0.05
0.26
Min
PCA9675
0.5
0.5
50
50
0
0
0
4
© NXP B.V. 2007. All rights reserved.
-
-
-
-
-
-
I
2
C-bus
f
1000
Max
0.45
450
120
120
is specified at
50
4
4
4
-
-
-
-
-
-
-
-
-
-
22 of 34
Unit
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s