SX1505I087TRT Semtech, SX1505I087TRT Datasheet - Page 16

• Manufacturer Part Number: SX1505I087TRT
• Description: IC GPIO EXP I2C 8CH 20UTQFN
• Manufacturer: Semtech

Specifications of SX1505I087TRT

• Interface: I²C
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UTQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SX1505I087TR

ADVANCED COMMUNICATIONS & SENSING
S: Start Condition
W: Write = ‘0’
R: Read = ‘1’
A: Acknowledge (sent by slave)
NACK: Non-Acknowledge (sent by master)
Sr: Repeated Start Condition
P: Stop condition
4.6
At start-up, the transition detection logic is reset, and NINT is released to a high-impedance state. The interrupt
mask register is set to 0xFF, disabling the interrupt output for transitions on all I/O ports. The transition flags are
cleared to indicate no data changes.
An interrupt NINT can be generated on any programmed combination of I/Os rising and/or falling edges through
the RegInterruptMask and RegSense registers.
If needed, the I/Os which triggered the interrupt can then be identified by reading RegInterruptSource register.
When NINT is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xFF in
RegInterruptSource (this will also clear corresponding bits in RegEventStatus register).
SX1506 also allows the interrupt to be cleared automatically when reading RegData register (Cf. RegAdvanced)
Example: We want to detect rising edge of I/O[1] on SX1505 (NINT will go low).
4.7
The SX1504, SX1505 and SX1506 offer a unique fully programmable logic functions like a PLD to give more
flexibility and reduce external logic gates used for standard applications.
Since the whole truth table is fully programmable, the SX1504, SX1505, and SX1506 can implement
combinatory functions ranging from the basic AND/OR gates to the most complicated ones with up to four 3-to1
PLDs or two 3-to-2 PLDs which can also be externally cascaded if needed.
In all cases, any IO not configured for PLD functionality retains its GPIO functionality while I/Os used by the PLD
have their direction automatically set accordingly.
Please note that while RegDir corresponding bits are ignored for PLD operation they may still be set to input to
access unused PLD inputs as normal GPI (PLD truth table can define some inputs to have no effect on PLD
output) and/or generate interrupt based on any of the PLD inputs or outputs bits.
4.7.1
The SX1504 I/Os can be configured to provide any combinational 2-to-1 logic function using I/O[0-2] whilst
retaining GPIO capability on I/O[3] OR provide a combinational 3-to-1 decode function using all 4 I/O ports.
Rev 2 – 30
1. We enable interrupt on I/O[1] in RegInterruptMask
2. We set edge sense for I/O[1] in RegSense
Interrupt (NINT)
Programmable Logic Functions (PLD)
Master operations
SX1504, SX1505 or SX1506 operations (Slave)
RegInterruptMask =“XXXXXX0X”
RegSenseLow =“XXXX01XX”
SX1504
th
August 2010
Figure 11 - 2-Wire Serial Interface, Read – Stop Separated Mode Operation
RegPLDMode
1:0
00
01
10
Table 7 – SX1504 PLD Modes Settings
Slave Address: 7 bit
Register Address: 8 bit
Data: 8 bit
PLD OUT
GPIO
GPIO
3
16
PLD OUT
PLD IN
GPIO
SX1504 I/Os
2
PLD IN
PLD IN
GPIO
1
SX1504/SX1505/SX1506
PLD IN
PLD IN
GPIO
0
4/8/16 Channel GPIO
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