MCP23008-E/P Microchip Technology, MCP23008-E/P Datasheet - Page 7

• Manufacturer Part Number: MCP23008-E/P
• Description: IC I/O EXPANDER I2C 8B 18DIP
• Manufacturer: Microchip Technology

Specifications of MCP23008-E/P

• Package / Case: 18-DIP (0.300", 7.62mm)
• Interface: I²C
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 1.7MHz
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Includes: POR
• Logic Family: MCP23008
• Propagation Delay Time: 50 ns
• Operating Supply Voltage: 1.8 V to 5.5 V
• Power Dissipation: 700 mW
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 1.8 V to 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Frequency: 1.7 MHz
• Mounting Style: Through Hole
• Output Current: 25 mA
• Output Voltage: 1.8 V to 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPAD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 1-1:
1.3.3.3
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer.
The sequence ends by the raising of CS.
The MCP23S08 address pointer will roll over to
address zero after reaching the last register address.
© 2007 Microchip Technology Inc.
SR
w
S
P
R
ADDR
D
D
OP
OUT
IN
- START
- RESTART
- STOP
- Write
- Read
- Data out from MCP23008
- Data into MCP23008
SPI Sequential Write/Read
- Device opcode
- Device address
Sequential
Sequential
Byte
Byte
MCP23008 I
S
S
S
S
S
S
OP
OP
OP
OP
OP
OP
2
C™ DEVICE PROTOCOL
W
R
W
W
W
W
ADDR
Byte and Sequential Write
Byte and Sequential Read
ADDR
ADDR
SR
SR
SR
OP
OP
MCP23008/MCP23S08
OP
SR
SR
P
SR
1.4
The hardware address pins are used to determine the
device address. To address a device, the correspond-
ing address bits in the control byte must match the pin
state.
• MCP23008 has address pins A2, A1 and A0.
• MCP23S08 has address pins A1 and A0.
The pins must be biased externally.
D
P
R
R
D
IN
OUT
D
D
W
OP
OP
IN
IN
OP
D
D
....
OUT
OUT
Hardware Address Decoder
ADDR
....
....
R
W
R
D
....
D
IN
OUT
D
D
D
D
P
OUT
IN
D
IN
OUT
P
D
IN
OUT
....
....
....
....
P
P
D
D
OUT
D
D
P
IN
OUT
IN
P
DS21919E-page 7
P
P
P
P