SAF7129AH/V1,518 NXP Semiconductors, SAF7129AH/V1,518 Datasheet - Page 20

• Manufacturer Part Number: SAF7129AH/V1,518
• Description: IC DIGITAL VIDEO ENCODER 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Encoderr

Specifications of SAF7129AH/V1,518

• Package / Case: 44-QFP
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935274073518; SAF7129AH/V1-T; SAF7129AH/V1-T

Philips Semiconductors
Table 16 Subaddress 3AH
Table 17 Subaddresses 42H to 44H and 48H to 4AH
Table 18 Subaddresses 45H to 47H and 4BH to 4DH
2004 Mar 16
ADDRESS
ADDRESS
Digital video encoder
4BH
4CH
4DH
42H
48H
43H
49H
44H
4AH
45H
46H
47H
BIT
7
6
5
4
3
2
1
0
SYMBOL
DEMOFF
KEY1UU
KEY2UU
KEY1UV
KEY1UY
KEY2UV
KEY2UY
KEY1LU
KEY2LU
KEY1LV
KEY2LV
KEY1LY
KEY2LY
CBENB
CSYNC
SYMP
MP2C
BYTE
BYTE
VP2C
0 = data from input ports is encoded; default state after reset
1 = colour bar with fixed colours is encoded
These 2 bits are reserved; each must be set to a logic 0.
0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default
state after reset
1 = horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at
MPEG port
0 = YC
1 = YC
0 = CVBS output signal is switched to CVBS DAC; default state after reset
1 = advanced composite sync is switched to CVBS DAC
0 = input data is twos complement from MPEG port fader input
1 = input data is straight binary from MPEG port fader input; default state after reset
0 = input data is twos complement from Video port fader input
1 = input data is straight binary from Video port fader input; default state after reset
Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 1 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE1
Default value of all bytes after reset = 80H.
Key colour 2 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 2 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE2
Default value of all bytes after reset = 80H.
B
B
C
C
video signal + (1
video signal + (1
R
R
-to-RGB dematrix is active; default state after reset
-to-RGB dematrix is bypassed
20
FADE1)
FADE2)
DESCRIPTION
DESCRIPTION
DESCRIPTION
MPEG signal
LUT values
SAF7129AH
Product specification